Cadence Design Systems Assigned Patent

Cadence Design Systems, Inc., San Jose, CA, has been assigned a patent (10,037,246) developed by Laws, Landon, Hughes, Anne, and MacLaren, John, Austin, TX, for a “system and method for memory control having self writeback of data stored in memory with correctable error.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system and method are provided for controlling access to memory to support processing of a master control operation. A data control portion is configured to carry out a plurality of data access operations on the memory device, including read, write, and read-modify-write operations for selectively addressed storage locations defined in the memory. An error control portion executes to detect error in a data segment as stored in the memory. The error control portion corrects a data segment read from the memory device for at least one type of detected error. A command control portion generates commands for actuating the data access operations of the data control portion. The command control portion includes a corrective writeback unit executable responsive to detection of correctable error in a data segment to actuate a read-modify-write operation to the data segment’s storage locations. The corresponding storage locations of the memory are thereby adaptively scrubbed.”

The patent application was filed on July 25, 2016 (15/218,279).