Cypress Semiconductor Assigned Five Patents

10-transistor non-volatile static random-access memory
using single non-volatile memory
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (9,997,237) developed by Tandingan, Joseph S, Still, David W., Colorado Springs, CO, Siman, Jesse J, San Jose, CA, and Ashokkumar, Jayant, Colorado Springs, CO, for a “10-transistor non-volatile static random-access memory using a single non-volatile memory element and method of operation thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory, NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line, (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.”

The patent application was filed on April 13, 2017 (15/487,071).

Memory devices having embedded hardware acceleration
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (9,965,387) developed by Maheshwari, Dinesh, Fremont, CA, for a “memory devices having embedded hardware acceleration and corresponding methods.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device can include an interface comprising a plurality of control and address connections and at least one set of data connections, memory circuits comprising a plurality of storage locations randomly accessible for read and write operations in response to an address value received on the address connections, and accelerator circuits coupled to the memory circuits and configured to perform at least one predetermined operation on data stored in the memory device to generate modified data for storage within the memory circuits in response to at least one command received on the interface, wherein the at least one command is supplemental to read and write commands executable by the memory device.”

The patent application was filed on July 11, 2011 (13/180,337).

Staggered start-up of predefined, random,
or dynamic number of flash memory devices
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (9,928,919) developed by Sundahl, Bradley Edman, O’Mullan, Sean Michael, Yancey, Gregory Charles, and Okin, Kenneth Alan, San Jose, CA, for a “method and apparatus for staggered start-up of a predefined, random, or dynamic number of flash memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory.”

The patent application was filed on May 19, 2015 (14/716,719).

Flash memory cells having trenched storage elements
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (9,917,211) developed by Zheng, Wei, Santa Clara, CA, Chang, Chi, Saratoga, CA, and Kim, Unsoon, San Jose, CA, for a “flash memory cells having trenched storage elements.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.”

The patent application was filed on April 16, 2014 (14/254,237).

Memory architecture having two independently controlled voltage pumps
Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (9,899,089) developed by Hirose, Ryan Tasuo, Colorado Springs, CO, Jenne, Fredrick B., Mountain House, CA, Raghavan, Vijay, Colorado Springs, CO, Kouznetsov, Igor G., San Francisco, CA, Ruths, Paul Fredrick, Woodland Park, CO, Zonte, Cristinel, Georgescu, Bogdan I., Gitlan, Leonard Vasile, Colorado Springs, CO, and Myers, James Paul, Woodinville, WA, for a “memory architecture having two independently controlled voltage pumps.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.”

The patent application was filed on September 24, 2013 (14/035,728).