Virident/HGST/WD Assigned Four Patents

Improve enterprise reliability through tracking I/O performance
metrics in non-volatile random access memory
Virident Systems Inc., San Jose, CA, an HGST/Western Digital company, has been assigned a patent (9,842,660) developed by Karamcheti, Vijay, Palo Alto, CA, Singhai, Ashish, Cupertino, CA, Narasimha, Ashwin, Sunnyvale, CA, Adiseshan, Muthugopalkrishnan, Sankaran, Viswesh, and Kumar, Ajith, Dodda Kammanahalli, India, for a “system and method to improve enterprise reliability through tracking I/O performance metrics in non-volatile random access memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for managing a non-volatile random-access memory, (NVRAM)-based storage subsystem, the method including: monitoring, by a slave controller on a NVRAM device of the NVRAM-based storage subsystem, an I/O operation on the NVRAM device, identifying, by the slave controller and based on the monitoring, at least one occurrence of error data, comparing, by the slave controller, a numeric aspect of the at least one occurrence of error data with a threshold setting, reporting, by the slave controller on the NVRAM device and to a master controller of the NVRAM-based storage subsystem, the at least one occurrence of error data in response to the numeric aspect crossing the threshold setting, and ascertaining, by the master controller of the NVRAM-based storage system, a physical location of a defect region on the NVRAM device where the error data has occurred by analyzing the reported at least one occurrence of error data.”

The patent application was filed on March 15, 2013 (13/841,026).

Application access to hybrid main memory
Virident Systems Inc., San Jose, CA, an HGST/Western Digital company, has been assigned a patent (9,836,409) developed by Karamcheti, Vijay, Palo Alto, CA, Okin, Kenneth A., Saratoga, CA, Ganapathy, Kumar, Los Altos, CA, Singhai, Ashish, and Parekh, Rajesh, Los Altos, CA, for a “seamless application access to hybrid main memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.”

The patent application was filed on January 6, 2016 (14/989,386).

Dynamic restriping in nonvolatile memory systems
Virident Systems Inc., San Jose, CA, an HGST/Western Digital company, has been assigned a patent (9,811,285) developed by Karamcheti, Vijay, Palo Alto, CA, Gowda, Swamy, Mishra, Rajendra Prasad, and Mondal, Shibabrata, Bangalore, India, for a “dynamic restriping in nonvolatile memory systems.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Data is stored as a first collection of memory blocks distributed across a first set of memory devices. It is determined that a first memory device in the first set is in a degraded state. Data is recovered corresponding to a first memory block in the first collection of memory blocks that is stored in the first memory device, which is configured to include a first number of memory blocks. The recovered data is stored in a second memory device as a new memory block, which is added to the first collection of memory blocks. The first memory device is removed from the first set and reconfigured with a second number of memory blocks that is less than the first number of memory blocks. Memory blocks in a second collection of memory blocks distributed across a second set of memory devices is stored in the reconfigured first memory device.”

The patent application was filed on March 11, 2016 (15/067,284).

Communicating to different types of memory modules in memory channel
Virident Systems Inc., San Jose, CA, an HGST/Western Digital company, has been assigned a patent (9,767,867) developed by Okin, Kenneth Alan, Saratoga, CA, Moussa, George, Dublin, CA, Ganapathy, Kumar, Karamcheti, Vijay, and Parekh, Rajesh, Los Altos, CA, for “methods of communicating to different types of memory modules in a memory channel.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A computer system is disclosed including a printed circuit board,( PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.”

The patent application was filed on September 2, 2013 (14/016,202).