eMemory Technology Assigned Eleven Patents

Non-volatile memory
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,830,991) developed by Lai, Tzu-Neng, Nantou County, Taiwan, for a “non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory includes a memory array and a controlling circuit. The memory array includes plural word lines and plural bit lines. The controlling circuit includes a processing circuit, a decoder, a driver, a timing controller and a sense amplifier. The decoder is connected with the processing circuit. The driver is connected with the decoder and the plural word lines. The timing controller is connected with the processing circuit. The sense amplifier is connected with the decoder, the timing controller and the plural word lines.”

The patent application was filed on December 1, 2016 (15/366,199).

Memory apparatus capable of preventing leakage current
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,824,727) developed by Huang, Kuo-Chun, Chiayi, Taiwan, for a “memory apparatus capable of preventing leakage current.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory apparatus includes a memory sector including N memory blocks and N local bit lines, a pre-charge circuit, and a program sector selector. Each of the N memory blocks includes a plurality of memory cells. Each of the N local bit lines is coupled to memory cells in a corresponding memory block. The pre-charge circuit is coupled to the N local bit lines. The program block selector is coupled to the N local bit lines and configured to apply a first voltage to a selected local bit line coupled to a selected memory block during a program mode of the selected memory block. Unselected local bit lines coupled to unselected memory blocks are pre-charged to a second voltage by the pre-charge circuit during the program mode of the selected memory block, thereby avoiding current leakages of the memory apparatus.”

The patent application was filed on September 8, 2016 (15/260,306).

Memory cell with low reading voltages
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,812,212) developed by Chen, Hsueh-Wei, Hsinchu, Taiwan, Chen, Wei-Ren, Pingtung County, Taiwan, and Sun, Wein-Town, Taoyuan, Taiwan, for a “memory cell with low reading voltages.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.”

The patent application was filed on January 18, 2017 (15/408,434).

Non-volatile memory cell
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,805,806) developed by Chen, Hsueh-Wei, Hsinchu, Taiwan, Chen, Wei-Ren, Pingtung County, Taiwan, and Sun, Wein-Town, Taoyuan, Taiwan, for a “non-volatile memory cell and method of operating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. The select gate is formed above the first diffusion region and the second diffusion region in a polysilicon layer. The floating gate is formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer. The assistant control gate is formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate.”

The patent application was filed on September 25, 2016 (15/275,454).

Memory device and single-byte data write
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,805,776) developed by Lin, Yih-Lang, Taipei, Taiwan, for a “memory device, peripheral circuit thereof and single-byte data write method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device, a peripheral circuit thereof and a single-byte data write method thereof are provided. The peripheral circuit includes a Y decoder, a page buffer, and a write circuit. The write circuit is coupled to a memory array and the page buffer through the Y decoder and receives a byte of program data. The write circuit is based on a memory address corresponding to the program data to receive a plurality of bytes of array data stored in the memory array through the Y decoder, and the read array data is written to page buffer through the Y decoder. Next, the program data is written to the memory array through the write circuit and Y decoder, and the array data is written to the memory array by the page buffer.”

The patent application was filed on December 15, 2016 (15/381,089).

Antifuse-type one time programming memory cell and array structure with same
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,799,662) developed by Wong, Wei-Zhe, and Wu, Meng-Yi, Hsinchu County, Taiwan, for a “antifuse-type one time programming memory cell and array structure with same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An antifuse-type OTP memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers the surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The second gate is connected with an antifuse control line. A third gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The third gate is connected with an isolation control line.”

The patent application was filed on January 13, 2016 (14/994,831).

Programming antifuse-type one time programmable memory cell
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,799,410) developed by Wong, Wei-Zhe, Hsinchu County, Taiwan, and Chen, Hsin-Ming, Hsinchu, Taiwan, for a “method for programming antifuse-type one time programmable memory cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse transistor. A first bit line voltage is transmitted to the antifuse transistor. A first voltage stress with a first polarity is provided to a gate oxide layer of the antifuse transistor to form a weak path between the gate terminal and the first drain/source terminal of the antifuse transistor. Secondly, a second program voltage is provided to the gate terminal of the antifuse transistor. A second bit line voltage is transmitted to the antifuse transistor. A second voltage stress with a second polarity is provided to the gate oxide layer of the antifuse transistor. Consequently, a program current is generated along the weak path to rupture the gate oxide layer above the first drain/source terminal.”

The patent application was filed on December 28, 2016 (15/392,348).

Memory cell with high endurance for multiple program operations
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,792,993) developed by Lo, Chun-Yuan, Wang, Shih-Chen, Taipei, Taiwan, and Ching, Wen-Hao, Hsinchu County, Taiwan, for a “memory cell with high endurance for multiple program operations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating gate. The common floating gate is coupled to the second floating gate transistor and the first floating gate transistor. The memory cell is programmed and erased through the common floating gate on the second floating gate transistor, and is read through the first floating gate transistor and the read transistor.”

The patent application was filed on January 16, 2017 (15/406,802).

Self-timed reset pulse generator and memory with self-timed reset pulse generator
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,792,968) developed by Chen, Chih-Chun, Taipei, Taiwan, Lin, Chun-Hung, Hsinchu, Taiwan, and Huang, Cheng-Da, Hsinchu County, Taiwan, for a “self-timed reset pulse generator and memory device with self-timed reset pulse generator.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A self-timed reset pulse generator includes a flip-flop, a tracking block, and a tracking circuit. The flip-flop receives an input signal and a feedback signal and outputting a reset signal. The tracking block has replicating cells coupled in series and replicates a structure in an external device. The tracking block has a first terminal and a second terminal. The first terminal and the second terminal are taking from the tracking block at a same location or two different locations. The tracking circuit unit receives the reset signal and receives the first terminal and the second terminal for respectively discharging the tracking block at the first terminal and sensing a voltage level at the second terminal as triggered by the reset signal. A track-out signal serving as the feed back signal is output to the flip-flop when the voltage level is less than or equal to a threshold.”

The patent application was filed on January 16, 2017 (15/406,800).

One time programmable non-volatile memory and read sensing
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,786,383) developed by Chen, Yung-Jui, New Taipei, Taiwan, for a “one time programmable non-volatile memory and read sensing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. Firstly, a selected memory cell of the memory array is determined, wherein one of the plural bit lines connected with the selected memory cell is a selected bit line and the other bit lines are unselected bit lines. Then, the unselected bit lines are precharged to a precharge voltage. Then, the selected bit line is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to at least one result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.”

The patent application was filed on March 6, 2017 (15/450,503).

Driving circuit for non-volatile memory
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (9,786,340) developed by Po, Chen-Hao, Hsinchu, Taiwan, for a “driving circuit for non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A driving circuit includes a driving stage with a first level shifter and a second level shifter. The first level shifter includes an input terminal receiving a first control signal, an inverted input terminal receiving an inverted first control signal, a first output terminal, and a second output terminal. The second level shifter includes an input terminal receiving a second control signal, an inverted input terminal receiving an inverted second control signal, a third output terminal, and a fourth output terminal. The first output terminal and the third output terminal are connected with each other to generate an output signal. The second output terminal and the fourth output terminal are connected with each other to generate an inverted output signal. Moreover, one of the first level shifter and the second level shifter is enabled according to an operation mode of the driving circuit.”

The patent application was filed on November 9, 2016 (15/347,158).