Intel Assigned Six Patents

Verifying cell programming in phase change memory
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,747,977) developed by Chu, Daniel J., Folsom, CA, Zeng, Raymond W., Sunnyvale, CA, and Rivers, Doyle, El Dorado Hills, CA, for a “methods and systems for verifying cell programming in phase change memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.“

The patent application was filed on March 14, 2013 (13/827,825).

Materials and components in phase change memory devices
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,741,930) developed by Soncini, Valter, Sesto San Giovanni, Italy, and Erbetta, Davide, Vimercate, Italy, for a “materials and components in phase change memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith are disclosed and described. Such electrodes can have a resistivity of from 10 to 100 mOhmcm.“

The patent application was filed on March 27, 2015 (14/671,204).

Electrode materials and interface layers to minimize chalcogenide interface
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,716,226) developed by Gealy, F. Daniel, Kuna, ID, Gotti, Andrea, Vaprio d’Adda, Italy, Colombo, Davide, Milan, Italy, and Chang, Kuo-Wei, Cupertino, CA, for a “electrode materials and interface layers to minimize chalcogenide interface.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about one nm and about ten nm.“

The patent application was filed on December 1, 2016 (15/366,364).

Reset current delivery in non-volatile random access memory
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,715,930) developed by Guliani, Sandeep K., and Pragyan, Ved, Folsom, CA, for a “reset current delivery in non-volatile random access memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory, (NVRAM), such as a phase change memory, (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device, a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device, and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.“

The patent application was filed on June 4, 2015 (14/731,212).

Dielectric thin film on electrodes for resistance change memory devices
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,698,344) developed by Kau, DerChang, Cupertino, CA, for a “dielectric thin film on electrodes for resistance change memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of the present disclosure describe techniques and configurations for increasing thermal insulation in a resistance change memory device, also known as a phase change memory, (PCM) device. In one embodiment, an apparatus includes a storage structure of a PCM device, the storage structure having a chalcogenide material, an electrode having an electrically conductive material, the electrode having a first surface that is directly coupled with the storage structure, and a dielectric film having a dielectric material, the dielectric film being directly coupled with a second surface of the electrode that is disposed opposite to the first surface. Other embodiments may be described and/or claimed.“

The patent application was filed on February 2, 2016 (15/013,517).

Path isolation in memory device
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,691,481) developed by Castro, Hernan A., Shingle Springs, CA, for a “path isolation in a memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory, (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.“

The patent application was filed on September 9, 2016 (15/261,301).