Everspin Assigned Patent

Everspin Technologies, Inc., Chandler, AZ, has been assigned a patent (9,740,431) developed by Alam, Syed M., Andre, Thomas, and Gogl, Dietmar, Austin, TX, for a “memory controller and method for interleaving DRAM and MRAM accesses.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.“

The patent application was filed on July 17, 2016 (15/212,271).