NVMe over Fabrics 1.0 and 1.2.1 Extensions Available From Avery Design Systems

Avery Design Systems Inc., in functional verification productivity solutions, announced availability of NVM Express over Fabrics 1.0 and NVM Express 1.2.1 extensions to its NVM-Xactor verification IP enabling verification of both NVMe over PCIe and NVMe over Fabrics designs.

NVM-Xactor is a verification solution for NVMe core and subsystem design. NVM-Xactor allows design and verification engineers to test the functionality of NVMe controller designs targeting memory or message transports.

The NVM-Xactor solution includes:

NVM host software BFM
NVM host and controller bus/fabric adaptor
Reference NVMe controller and adaptor
Producer-consumer scoreboard
Compliance testsuite
Protocol checks
Protocol analyzer tracker
Functional coverage model
Works with any PCIe and AXI IP or VIP
Developed in Native SystemVerilog/UVM

“NVMe over Fabrics is an essential technology to scale-out NVMe storage connectivity using the simplicity and efficiency of an End-to-End NVMe model“, said Chris Browy, VP sales and marketing, Avery. “Our industry lading NVM-Xactor now spans the spectrum of client to enterprise NVMe design applications“.

“CNEX Labs has effectively employed the Avery NVMe and PCIe VIP for the development of our semiconductor solutions. Using these models and compliance testsuites has helped us to achieve comprehensive, high quality verification for our ASIC designs“, said Justin Heindel, VP Product, CNEX Labs, Inc. “The technical support has been excellent, and we look forward to using Avery VIP products on future NVMe designs.“

NVM-Xactor works in conjunction with various physical transport layers including Avery’s PCI-Xactor, PCI Express and AMBA Verification IP solutions or other fabric interfaces such as Ethernet, FC, or IB to supply a complete NVMe subsystem verification environment. A NVM bus/fabric adaptor layer provides memory and RDMA transport access interface by the NVM host software BFM to the NVMe Controller via the full bus/fabric protocol or through a bypass mode yielding faster simulation performance for large data movement. A reference NVMe controller layer also supports core-level verification by emulating the NAND flash backend subsystem.