Cypress Semiconductor Assigned Patent

Cypress Semiconductor Corporation, San Jose, CA, has been assigned a patent (9,159,568) developed by Lee, Chungho, Sunnyvale, CA, Zheng, Wei, Santa Clara, CA, Chang, Chi, Saratoga, CA, Kim, Unsoon, and Kinoshita, Hiroyuki, San Jose, CA, for a “method for fabricating memory cells having split charge storage nodes.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.“

The patent application was filed on December 15, 2006 (11/639,666).