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Avalanche Technology Assigned Four Patents

Perpendicular STT-MRAM design and manufacturing

Avalanche Technology, Inc., a developer of memory technology and enterprise solid state storage solutions, has been awarded or granted key patents for its non-volatile spin torque transfer magnetic random access memory (STT-MRAM) technology in areas of perpendicular STT-MRAM and MRAM integration and manufacturing. 

These patents bolster the game-changing advances of Avalanche’s IP portfolio related to STT-MRAM memory MTJ cell design and its manufacturing methods.
 
There are tremendous opportunities for non-volatile memories to replace volatile memories. This will drive major changes in computer architectures and enable entire new types of products for the enterprise, client and consumer industries,” said Tom Coughlin, president, Coughlin Associates, a storage consultancy. “Avalanche’s extensive patent portfolio and focus on high yield STT-MRAM on 300mm CMOS wafers are factors that should enable the market shift from volatile to non-volatile memory.”
 
In area of perpendicular STT-MRAM, Avalanche IP covers perpendicular MTJ (pMTJ) stack designs that deliver high performance pMTJ memory cells as well as fundamental techniques that enhance Perpendicular STT-MRAM memory, high-density extendibility and long-term reliability. 

There are three key patents in this area:

  • Magnetic Random Access Memory With Switching Assist Layer (USPTO #8,492,860) – high speed STT-MRAM MTJ cell design with switching mechanism that was proven in real devices to achieve switching speed better than 300 picoseconds, while also accomplishing superior operability and manufacturability.
  • Method For Magnetic Screening Of Arrays Of Magnetic Memories (USPTO #8,553,452) – fundamental method to effectively identify and eliminate soft-error-prone cells at wafer level to greatly enhance STT-MRAM product throughput, yield and long-term reliability.
  • Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) Device With Shared Transistor And Minimal Written Data Disturbance (USPTO #8,611,145) – fundamental method to enable STT-MRAM functionality at extreme data densities where MTJ cell writability is enhanced by acquiring writing power from adjacent unused MTJ cells.

In the area of MRAM integration and manufacturing, Avalanche IP covers advanced STT-MRAM cell designs utilizing CMOS structures that are less complex, more scalable and have lower manufacturing costs than Fin-FET designs. Avalanche has distinctive and foundry-proven STT-MRAM manufacturing methods and experience, including MTJ stacking, MTJ etching, MTJ-CMOS integration and tooling with 300mm wafers.
 
MRAM manufacturing process for a small MTJ design with a low programming current requirement (USPTO#8,542,526) – discloses a manufacturing method to pattern small MTJ elements with enhanced extendibility and scalability to 1xnm for high-density applications.
 
These patent awards are representative of the strong impact Avalanche will have related to STT-MRAM, perpendicular MTJ cell design and its manufacturing methods,” said Yiming Huai, PhD., VP of technology, Avalanche Technology. “The Avalanche engineering team continues to deliver a broad portfolio of patents that ensure the unique market advantages of our perpendicular STT-MRAM technology.”

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