Synopsys DesignWare IP for PCIe 3.0 Passes PCI-SIG Compliance Workshop

Highlights

• Synopsys’ DesignWare digital controller and PHY IP for PCIe 3.0 passed PCI-SIG‘s three required Gold Tests and completed interoperability with more than the requisite 80% of the devices at the workshop
• Complete PCIe 3.0 solution, including PHY, controller and verification IP, reduces integration risk while minimizing time-to-market
• PCIe 3.0 controllers, optimized for high performance, low latency and low gate counts, support x1 to x16 lanes and ARM AMBA AXI4, AXI3, and AHB interconnect
• Energy-efficient PCIe 3.0 PHY offers high-performance analog front-end for signal integrity and is available in 28nm process nodes

Synopsys, Inc., providing software, IP and services used to accelerate innovation in chips and electronic systems, announced that its DesignWare PHY and digital controller IP for the PCI-SIG PCIe 3.0 is the first complete solution from a single vendor to pass compliance testing at the first PCI-SIG compliance workshop for PCIe 3.0.

The PCIe 3.0 specification increases the operating rate to 8 gigatransfers per second (GT/s), effectively doubling the bandwidth over PCIe 2.0 to address the performance requirements of data center, storage and networking applications.

To achieve compliance, the DesignWare PHY and controller IP passed PCI-SIG’s three required Gold Tests: the electrical tests, the Protocol Test Card (PTC) and the PCIeCV software tests. In addition, the DesignWare PHY and controller IP demonstrated interoperability with more than 80% of the devices at the workshop, exceeding interoperability requirements. By providing a complete and compliant IP solution for PCIe 3.0, Synopsys enables designers to incorporate the PCIe 3.0 interface into SoCs with less risk and improved time-to-market, while helping to ensure product interoperability.

"As the leader in application-intelligent 10GbE network interface software and hardware, we rely on Synopsys to provide us with high-performance PCIe IP that helps us differentiate our products in the market," said Andre Chartand, VP of engineering at Solarflare Communications, Inc. "Synopsys’ high-quality IP for PCIe 3.0, including the scalable I/O virtualization support necessary for our cloud and software defined networking offerings, as well as the company’s superior technical support, were instrumental in the silicon success of our next-generation SFN7000 design."

"Teledyne LeCroy has collaborated with Synopsys through multiple generations of DesignWare PCIe IP to ensure interoperability and standards compliance," said John Wiedemeier, PCIe product marketing manager at Teledyne LeCroy. "Synopsys’ ongoing commitment to performing extensive compliance testing to the latest specifications, including their recent success at the PCI-SIG Compliance Workshop, lowers the barrier for designers to incorporate high speed PCIe interfaces into their chips."

The complete DesignWare IP for PCIe solution includes PHYs, controllers and verification IP. DesignWare IP for PCIe has been used in more than 750 designs, with more than 80 for PCIe 3.0. The full-featured, performance digital controller IP for PCIe 3.0 provides an optional interface to connect to ARM AMBA AXI4, AMBA AXI3 or AMBA AHB on-chip interconnect using the DesignWare IP for PCIe Bridge, which allows designers to add PCIe 3.0 functionality to their SoCs. The PHYs substantially exceed the PCIe electrical specifications in key performance areas such as jitter margin and receive sensitivity, which enable a more reliable PCIe link.

"As an active member of the PCI-SIG since 2003, Synopsys understands the importance of contributing to the PCIe specification working groups and participating in compliance testing as part of the ecosystem enablement," said Al Yanes, PCI-SIG president."Synopsys’ compliance to the latest version of the PCIe 3.0 specification helps ensure compatibility among products incorporating PCIe while facilitating the widespread adoption of PCIe 3.0."

"To maintain our leadership in PCIe IP, we make continuous investments in new product features and conduct rigorous compliance testing to ensure our IP meets the latest specifications," said John Koeter, VP marketing for IP and systems at Synopsys. "We have moved aggressively to align our PCIe roadmap with the industry’s needs by providing PCIe 3.0 support since the 0.5 version of the specification. Early availability enabled our customers to meet their aggressive time-to-market requirements. Achieving this latest compliance milestone gives designers confidence that they can incorporate a complete PCIe solution into their SoCs that will meet their full performance and interoperability requirements."

The DesignWare Controller for PCIe 3.0 is available. The DesignWare PHY IP for PCIe 3.0 is available in multiple 28nm technology nodes.