Chelsio Terminator 5, 5th-Gen of Ethernet ASIC

Chelsio Communications, Inc. announced Terminator 5, the fifth generation of its high performance Ethernet silicon technology.

The Terminator 5 (T5) ASIC is built upon the latest iteration of Chelsio’s protocol-rich high speed network processing architecture, and leverages an industry-proven design, which has been deployed with more than 200 OEM platforms and more than 400,000 ports shipped worldwide.

Launching two years after the T4 ASIC, the T5 moves the architecture into 40GbE speeds, and prepares the transition to 100GbE expected by 2015.

T5 is an integrated, hyper-virtualized 10/40GbE controller with offload support of a complete Unified Wire solution comprising NIC, TOE, iWARP RDMA, iSCSI, FCoE and NAT.

It provides both low latency (sub 1μs through hardware) and high bandwidth, limited only by the PCI bus. Furthermore, it scales to true 40Gb line rate operation from a single TCP connection to thousands of connections, and allows simultaneous low latency and high bandwidth operation thanks to multiple physical channels through the ASIC.

Designed for high performance clustering, storage and data networking, the T5 enables fabric consolidation by simultaneously supporting TCP/IP and UDP/IP socket applications, RDMA applications and SCSI applications at wire speed, thereby allowing IB and FC applications to run unmodified and concurrently over standard Ethernet. This will result in tremendous savings in the data center by avoiding the need for IB or FC adapters, cabling, switches and gateways. The API used for the complete software suite (Linux, Windows and FBSD) in current T4 installations is the same for the T5 chip and upcoming 100Gb capable versions, leveraging the software investment made in T4 deployments.

T5 establishes a new milestone for SAN performance, finally moving past FC performance. With T5, true 40Gb SAN throughput, more than 3x the latest FC speeds, is now enabled via offloaded iSCSI without waiting for specialized FCoE switches. T5 is further expected to improve storage IO performance from the current record of 2.1M IOPS held by the T4 silicon.

T5 also establishes a milestone for Ethernet clustering performance. While recent comparisons of IB-FDR and T4 iWARP RDMA show the two at parity (LAMMPS, LS-DYNA, HPL and WRF on iWARP vs IB FDR) with half the latency and 4x the bandwidth of T4, T5 is expected to exceed IB-FDR performance. Thanks to the reliability provided by hardware offloaded TCP/IP, the benefits of T5 RDMA include eliminating the scalability and cabling and noise issues associated with IB-FDR.

With a specific design focus on low latency and small packet processing performance, T5 also enables a performance milestone for high frequency trading and other latency sensitive applications.

Given the high integration of T5, the ability to concurrently run all the different protocols at performance levels, and the feature set that addresses all of Ethernet’s market segments, this silicon enables OEMs to converge on a single vendor for all their connectivity needs.

The market for 40GbE is expected to ramp quickly. Crehan Research forecasts 40GbE server adapters and LOMs will exceed $600 million by 2017.

"The Terminator 5 ASIC is an important evolutionary step for Chelsio, bringing all the offload, virtualization, and switching capabilities of the existing T4 chip to 40Gbps performance levels," said Bob Wheeler, senior analyst at The Linley Group. "The arrival of the T5 should accelerate the convergence of networking, storage, and clustering around 40G Ethernet."

T5 Architectural Features
The T5 ASIC is built around a scalable and programmable protocol-processing engine. Much of the processing of the offloaded protocols is implemented in microcode running on a proprietary pipelined data-flow engine. The pipeline supports cut-through operation for both transmit and receive paths for minimum latency, and the transport processor is designed for wire-speed operation at small packet sizes, regardless of the number of TCP connections.

Some features of the T5:

• PCIe v3.0 x8 host interface
• 2xDDR-3 memory interfaces
• 4x100M/1G/10G or 2x40GE ports
• Designed for low latency, high bandwidth and packet processing rate
• NIC/TOE/iWARP RDMA/iSCSI/FCoE/NAT offload
• TOE/iWARP RDMA/iSCSI/FCoE port to port, and adapter to adapter failover
• SR-IOV 8PF/128VF + VEPA/VEB 802.1Qbg/h offload virtualization
• Integrated OpenFlow ready virtual Ethernet switch
• T10-DIF/DIX protection support for both FCoE and iSCSI

The T5 is designed in 45nm SOI CMOS process technology and packaged in a 31x31mm, 899-pin FCBGA. Customer samples are available in Q1 and volume quantities in Q2. Driver development and reference design kits are available.