Evatronix With High Speed Inter-Chip Compatible PHY IP

Evatronix SA, provider of USB-IF certified solutions for SuperSpeed USB 3.0 and USB 2.0 IP, have announced a High Speed Inter-Chip (HSIC) compatible PHY IP for power and area savings in USB 2.0 chip-to-chip connections.

Implementation of the HSIC technology enables setting up a direct connection on a PCB board between a USB Host chip and other on-board USB devices. The HSIC standard features less power consumption thanks to elimination of requirements to support long external USB cables while remaining USB protocol compliant and thus USB software compatible. The possibility for straightforward use of all the available USB software gives HSIC an advantage over other inter-chip connection standards, like I2C.

"The introduction of the USBHSIC-PHY is the next step in the Evatronix strategy of delivering complete USB solutions," said Wojciech Sakowski, Evatronix CEO. "With a silicon-proven suite of controllers, software stacks and OS drivers already in our portfolio, we are now complementing our offering with the USBHSIC-PHY to enable straightforward implementation of the USB 2.0 chip-to-chip connectivity with all components from a single IP vendor."

Through the implementation of a 240MHz DDR interface the HSIC standard provides support for the 480Mbps data transfer of the USB protocol. By elimination of 3.3 and 5V signaling the HSIC interface enables significant silicon area and power savings in comparison to standard cable USB 2.0 PHYs.

The Evatronix USBHSIC-PHY logic macro is available on the LFoundry 150nm process with the possibility to port it to any technology node from 65 to 180nm.