Synopsys DesignWare USB 3.0 IP Receives USB-IF Certification

Synopsys, Inc., in software and IP for semiconductor design, verification and manufacturing, announced that its DesignWare SuperSpeed USB (USB 3.0) Solution including Controller and PHY IP passed the USB Implementers Forum (USB-IF) SuperSpeed USB certification.

          
In the picture, USB 3.0 PHY test chip
           on the daughter board is on the right.

To achieve certification, the IP must pass protocol, electrical, and interoperability tests for SuperSpeed USB (USB 3.0, 5 Gbps) and Hi-Speed USB (USB 2.0, 480 Mbps). Synopsys created a fully integrated USB 3.0 IP solution, optimizing all speed modes into a single USB 3.0 solution. This unique implementation enables designers to reduce area, pin count and power compared to separate USB 2.0 and SuperSpeed USB-only designs. Furthermore, the integrated DesignWare SuperSpeed USB IP significantly lowers integration risk and effort by not requiring designers to manage two distinct USB 2.0 and USB 3.0 data paths in their system-on-chips (SoCs). Synopsys showed its certified DesignWare SuperSpeed USB IP solution at the SuperSpeed USB Developer’s Conference.

"Passing certification is important as it demonstrates that the IP meets USB-IF interoperability standards and is compliant to the USB 3.0 specification," said Jeff Ravencraft, president and chairman, USB-IF. "Certification of IP building blocks is an important step in the evolution of SuperSpeed USB technology, it assures designers that the solution interoperates with existing USB products while providing the speed and power benefits that SuperSpeed USB offers."

"As a leading provider of graphics over USB 2.0, it was critical that we select a trusted USB IP provider for the development of our next-generation high-definition over USB 3.0 platform," said Dennis Crespo, executive vice president of marketing, DisplayLink. "We chose Synopsys because of their established track record in delivering proven and compliant USB IP solutions which enables us to reduce the risk of incorporating a new interface into our design and quickly get our differentiated product to the market."

"For the past 15 years, Synopsys has been delivering high-quality USB IP solutions which have been integrated in more than 2000 designs," said John Koeter, vice president of marketing, Solutions Group at Synopsys. "We leveraged our extensive experience in USB 2.0 and high-speed serial interfaces to develop our USB 3.0 IP solution that supports all four transfer speeds defined in the USB 3.0 specification. This gives designers a reliable and low-risk path to silicon-success for their USB 3.0 products."

The DesignWare SuperSpeed USB device controller and PHY IP is based on Synopsys’ technology leading Hi-Speed USB products, which have been silicon-proven in thousands of designs and are shipping in volume production. Optimized for low power, the DesignWare SuperSpeed USB device controller is architected to allow designers to maximize battery life by using dual power rails. The DesignWare SuperSpeed USB PHY consists of integrated high-speed digital and analog blocks, PLL and I/O pads, which are delivered as GDSII for advanced foundry processes. This saves designers considerable time, cost and the risk of acquiring and integrating the IP separately. The DesignWare SuperSpeed USB Verification IP has built-in support for the VMM methodology, enabling designers to quickly verify connectivity between integrated IP and the SoC. The Linux drivers and SystemC transaction-level models in the DesignWare SuperSpeed USB virtual prototype allow designers to begin software development in parallel with IP integration, months before hardware and FPGA prototypes are ready. This significantly reduces the length of the product design cycle.

Availability
The DesignWare SuperSpeed USB Device, Hub, Host and Dual-Role Device Controllers, virtual prototype and driver IP are available now. The DesignWare SuperSpeed USB PHY IP is available in leading 65-nanometer (nm) and 130-nm process technologies now with support for 28-nm and 40-nm process technologies expected to be available in the second half of 2010.