R&D: Fast and Accurate Prediction of Electrical Characteristics of Next-Gen Node 3D NAND Flash Memory Using Transfer Learning

IEEE Transactions on Electron Devices has published an article written by Hyundong Jang, Samsung Electronics Company, Hwaseong-si, Gyeonggi-do, South Korea, Soomin Kim, Kyeongrae Cho, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South Korea, Kihoon Nam, SKhynix Inc, Icheon-si, Gyeonggi-do, South Korea, Donghyun Kim, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South Korea, Hyeok Yun, SKhynix Inc, Icheon-si, Gyeonggi-do, South Korea, Seungjoon Eom, and Rock-Hyun Baek, Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South Korea.

Abstract: “Electrical characteristics of scaled 3-D NAND cells for next-generation node development were predicted using transfer learning with limited data. The NAND cell structure parameters were considered as the inputs, and outputs included key electrical characteristics, such as cell V_t, the difference in V_t between the initial and programming states (ΔV_t), subthreshold swing (SS), and ON-current (I_ON). A multilayer perceptron (MLP) model comprising four hidden layers and focusing on large NAND cells (25 nm gate length) with 2000 data points served as a pre-trained model. The transfer model leveraged pre-trained knowledge to predict the electrical characteristics of smaller cells (19 nm gate length) with 500 data points without weight and bias training. Evaluation of test data exhibited remarkable accuracy with both the mean and standard deviation below 3%, proving the model’s effectiveness despite limited data. In addition, a comprehensive evaluation was conducted by comparing the performance of the model with variations in the dataset size and the presence of transfer learning, highlighting the effectiveness and advantages of transfer learning. Transfer learning could provide detailed structure information of the next node for engineers and expedite device development, resulting in significant time and cost savings.“