R&D: Compact Modeling of Trap-Assisted Tunneling Current in 3-D NAND Flash Memory

IEEE Transactions on Electron Devices has published an article written by Hyungjun Jo, Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea, and Hyungcheol Shin, Department of Electrical and Computer Engineering, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea, and Integra Semiconductor Ltd, Seoul, South Korea.

Abstract: “In this research, a compact model is proposed for trap-assisted tunneling (TAT) currents in 3-D NAND flash memory during erase/write (EW) cycling. Using the trap spectroscopy by charge injection and sensing (TSCIS) technique, the average trap density and trap energy level are extracted and applied in the TAT model. The compact model integrates band-to-trap tunneling (BT), trap-to-band tunneling (TB), and trap-to-trap tunneling (TTT) mechanisms. In BT and TTT, tunneling to trap occurs only when the trap energy level is aligned with or below the injection level. Modified tunneling equations are used to address misaligned trap energy levels in TTT. The compact model demonstrates good agreement with measurement data across various word-line (WL) voltages and cycling conditions.“