STMicroelectronics Assigned Thirteen Patents

Method for managing zone of sensitive data in flash memory
STMicroelectronics (Alps) SAS, Grenoble, France, has been assigned a patent (12271607) developed by Benhammadi; Jawad, Pont de Claix, France, for a “method for managing a zone of sensitive data in a flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.”

The patent application was filed on 2023-05-16 (18/318416).

Phase change memory device with improved retention characteristics and related method
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (12266402) developed by Petroni; Elisa, Sesto San Giovanni, Italy, and Redaelli; Andrea, Milan, Italy, for “phase change memory device with improved retention characteristics and related method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A phase change memory element has a memory region, a first electrode and a second electrode. The memory region is arranged between the first and the second electrodes and has a bulk zone and an active zone. The memory region is made of a germanium, antimony and tellurium based alloy, wherein germanium is in a higher percentage than antimony and tellurium in the bulk zone of the memory region. The active zone is configured to switch between a first stable state associated with a first memory logic level and a second stable state associated with a second memory logic level. The active zone has, in the first stable state, a uniform, amorphous structure and, in the second stable state, a differential polycrystalline structure including a first portion, having a first stoichiometry, and a second portion, having a second stoichiometry different from the first stoichiometry.”

The patent application was filed on 2022-11-23 (17/993118).

Phase-change memory
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (12262649) developed by Boivin; Philippe, Venelles, France, for a “phase change memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.”

The patent application was filed on 2021-10-22 (17/508754).

Sense amplifier architecture for NVM storing coded information
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (12260910) developed by Disegni; Fabio Enrico Carlo, Spino d’adda, Italy, Carissimi; Marcella, Treviolo, Italy, Tomasoni; Alessandro, Sotto il Monte Giovanni XXIII, Italy, and Lo Iacono; Daniele, Bergamo, Italy, for a “sense amplifier architecture for a Non-volatile Memory storing coded information.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.”

The patent application was filed on 2022-12-29 (18/148380).

SRAM cell layout including arrangement of multiple active regions and multiple gate regions
STMicroelectronics International N.V., Geneva, Switzerland, has been assigned a patent (12250804) developed by Ahmed; Shafquat Jahan, Greater Noida, India, and Janardan; Dhori Kedar, Ghaziabad, India, for a “SRAM cell layout including arrangement of multiple active regions and multiple gate regions.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.”

The patent application was filed on 2023-08-23 (18/454471).

Protection system and method for memory
STMicroelectronics (Grand Ouest) SAS, Le Mans, France, has been assigned a patent (12242393) developed by Jaouen; Michel, Yvre l’eveque, France, for a “protection system and method for a memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment system for protecting a memory comprises security software configured to determine, from an exception generated during an unauthorized action attempt in the memory, whether the security software can perform the action.”

The patent application was filed on 2020-09-02 (17/010072).

In-memory compute array with integrated bias elements
STMicroelectronics International N. V., Geneva, Switzerland, has been assigned a patent (12243584) developed by Grover; Anuj, New Delhi, India, Roy; Tanmoy, Grenoble, France, and Chawla; Nitin, Noida, India, for an “in-memory compute array with integrated bias elements.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.”

The patent application was filed on 2023-02-10 (18/167580).

Selective bit line clamping control for in-memory compute operation where simultaneous access is made to plural rows of SRAM
STMicroelectronics International N. V., Geneva, Switzerland, has been assigned a patent (12237007) developed by Dhori; Kedar Janardan, Ghaziabad, India, Rawat; Harsh, Haryana, India, Kumar; Promod, Greater Noida, India, Chawla; Nitin, and Ayodhyawasi; Manuj, Noida, India, for a “selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM).“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.”

The patent application was filed on 2022-06-29 (17/852567).

Embedded system
STMicroelectronics Belgium, Machelen, Belgium, has been assigned a patent (12217057) developed by Ahssini; Youssef, Vilvoorde, Belgium, and Restiau; Guy, Ramillies, Belgium, for an “embedded system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embedded systems and methods of reading or writing data or instructions of at least one application in a non-volatile memory are disclosed. A method includes reading or writing data or instructions of at least one application in a non-volatile memory of an embedded system. The data or instructions transit through a memory area and are interpreted by a distinct program of an operating system of the embedded system.”

The patent application was filed on 2023-06-27 (18/342150).

Insulation of phase-change memory cells
STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (12213392) developed by Boivin; Philippe, Venelles, France, for an “insulation of phase-change memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Memory devices and methods of manufacturing such devices are provided herein. In at least one embodiment, a memory device includes a plurality of phase-change memory cells. An electrically-insulating layer covers lateral walls of each of the phase-change memory cells, and a thermally-insulating material is disposed on the electrically-insulating layer and covers the lateral walls of the phase-change memory cells.”

The patent application was filed on 2021-06-29 (17/362670).

Modular memory architecture with more significant bit sub-array word line activation in single-cycle read-modify-write operation dependent on less significant bit sub-array data content
STMicroelectronics International N.V, Geneva, Switzerland, has been assigned a patent (12210754) developed by Verma; Praveen Kumar, Greater Noida, India, for a “modular memory architecture with more significant bit sub-array word line activation in single-cycle read-modify-write operation dependent on less significant bit sub-array data content.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A first word line signal is applied to a selected one of the first word lines to read less significant bits from the first sub-array, and a mathematical operation is performed on the read less significant bits to produce modified less significant bits that are written back to the first sub-array. If the read less significant bits are saturated, a second word line signal is applied to a selected one of the second word lines to read more significant bits from the second sub-array, and a mathematical operation is performed on the read more significant bits to produce modified more significant bits that are written back to the second sub-array.”

The patent application was filed on 2022-10-13 (17/965243).

Accessing memory cells, corresponding circuit and data storage device
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (12205651) developed by Lo Giudice; Gianbattista, Pedara, Italy, and Conte; Antonino, Tremestieri Etneo, Italy, for a “method for accessing memory cells, corresponding circuit and data storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.”

The patent application was filed on 2022-09-08 (17/940753).

Bit-cell architecture based in-memory compute
STMicroelectronics International N.V, Geneva, Switzerland, has been assigned a patent (12183424) developed by Rawat; Harsh, Faridabad, India, Dhori; Kedar Janardan, Ghaziabad, India, Kumar; Promod, Greater Noida, India, Chawla; Nitin, and Ayodhyawasi; Manuj, Noida, India, for a “bit-cell architecture based in-memory compute.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.”

The patent application was filed on 2022-09-27 (17/954060).