Sunrise Memory Assigned Five Patents

Quasi-volatile memory with reference bit line structure
Sunrise Memory Corp., San Jose, CA, has been assigned a patent (12245429) developed by Petti; Christopher J., Mountain View, CA, for a “quasi-volatile memory with reference bit line structure.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embodiments, the semiconductor memory device includes a reference bit line structure to provide a reference bit line signal for read operation. The reference bit line structure configures word line connections to provide a reference bit line to be used with a storage transistor being selected for read access. The reference bit line structure provides a reference bit line having the same electrical characteristics as an active bit line and is configured so that no storage transistors are selected when a word line is activated to access a selected storage transistor associated with the active bit line.”

The patent application was filed on 2022-01-14 (17/576416).

3D vertical Nor flash thin-film transistor strings
Sunrise Memory Corp., San Jose, CA, has been assigned a patent (12245430) developed by Harari; Eli, and Yan; Tianhong, Saratoga, CA, for a “three-dimensional vertical Nor flash thin-film transistor strings.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.”

The patent application was filed on 2023-07-19 (18/223994).

Memory controller including write staging buffer to manage write requests for high capacity memory circuit with large number of independently accessible memory banks
Sunrise Memory Corp., San Jose, CA, has been assigned a patent (12210749) developed by Fux; Shay, Kfar Yona, Israel, Goldenberg; Sagie, Gaaton, Israel, and Yagev; Amotz, Sdot, Yam, Israel, for a “memory controller including a write staging buffer to manage write requests for a high capacity memory circuit with large number of independently accessible memory banks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system includes a memory device including an array of storage transistors for storing data where the storage transistors are organized in multiple memory banks, each memory bank including multiple memory pages; and a control circuit configured to interact with the memory device to perform read and write operations. The control circuit includes a read queue configured to store active read requests for reading data from the memory device, a write queue configured to store active write requests for writing data to the memory device, and a write staging buffer configured to store pending write requests received by the control circuit and to transfer the pending write requests to the write queue to maximize the number of active write requests that are addressed to different memory banks of the memory device.”

The patent application was filed on 2023-07-24 (18/357948).

3D memory structure fabrication using channel replacement
Sunrise Memory Corp., San Jose, CA, has been assigned a patent (12205645) developed by Kamisaka; Shohei, Kanagawa, Japan, and Purayath; Vinod, Sedona, AZ, for a “three-dimensional memory structure fabrication using channel replacement.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A process for fabricating a three-dimensional NOR memory string of storage transistors implements a channel-last fabrication process with channel replacement using silicon germanium (SiGe). In particular, the process uses silicon germanium as a sacrificial layer, to be replaced with the channel material after the charge-storage layer of the storage transistors is formed. In this manner, the channel region is prevented from experiencing excessive high-temperature processing steps, such as during the annealing of the charge-storage layer.”

The patent application was filed on 2022-04-18 (17/723204).

Memory device including reference bit line for increasing read operation accuracy
Sunrise Memory Corp., San Jose, CA, has been assigned a patent (12200927) developed by Nosho; Yosuke, Ohashi; Takashi, Tokyo, Japan, Kamisaka; Shohei, and Hirotani; Takashi, Kanagawa, Japan, for a “memory device including reference bit line for increasing read operation accuracy.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes source-drain structure bodies and gate structure bodies arranged along a first direction, and global word lines. The source-drain structure body includes a bit line, and first to third semiconductor layers. The first and second semiconductor layers are of first conductivity type and the first semiconductor layer is connected to the bit line. The third semiconductor layer of a second conductivity type contacts the first and second semiconductor layers. The gate structure body includes a local word line and a charge storage film. A first source-drain structure body includes a bit line forming a first reference bit line. A first global word line connects to the local word lines in the gate structure bodies formed on both sides of the first reference bit line and to the local word lines formed in alternate gate structure bodies that are formed between the remaining plurality of source-drain structure bodies.”

The patent application was filed on 2022-01-14 (17/576544).