R&D: Investigation of Memory Operations in 3D NAND Flash with More Realistic Geometry with Wavey Channel in Tapered Channel Hole

Journal of Electrical Engineering & Technology has published an article written by Hyun-Seo Oh, Yun-Jae Oh, Hyeongjun So, Jueun Kim, Department of Electronic Engineering, Myongji University, Yongin-si, Gyeonggi-do, 17058, Republic of Korea, Soomin Kim, So Won Son, Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul, 03760, Republic of Korea, Tae Hun Kim, I-Nano FAB Center, Incheon National University, Incheon, 22012, Republic of Korea, and Semiconductor Research Center, Samsung Electronics, Yongin-si, 17113, Gyeonggi-do, Republic of Korea, Daewoong Kang, Department of Next Generation Semiconductor Convergence and Open Sharing System, Seoul National University, Seoul, 08826, Republic of Korea, Seongjae Cho, Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul, 03760, Republic of Korea, and Il Hwan Cho, Department of Electronic Engineering, Myongji University, Yongin-si, Gyeonggi-do, 17058, Republic of Korea.

Abstract: “Recent developments in 3D NAND flash memory technology have greatly enhanced memory capacity and integration density compared to 2D NAND, addressing the growing demand for high-performance storage in various fields. This study investigates the effects of wavey shape factor (WF) and taper angle on the programming characteristics of 3D NAND flash memory by a series of technology computer-aided design (TCAD) device simulations. Our analysis reveals that both WF and taper angle significantly impact the threshold voltage (V_TH) and trapped charge in memory cells. Specifically, as the taper angle increases, the bottom memory cell experiences more pronounced variations in V_TH and trapped charge due to a smaller channel radius and altered electric field distribution. This study also shows that larger taper angles affect the tunneling oxide region more significantly than the blocking oxide region, leading to greater performance variations. These investigations highlight the need for optimized design strategies to minimize performance non-uniformity and improve the reliability of next-generation NAND memory technologies.“