Winbond Electronics Assigned Seven Patents

Erasing flash memory
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (12237017) developed by Cheng; Lung-Chi, Kuo; Ying-Shan, Huang; Jun-Yao, Cheng; Ju-Chieh, and Chuang; Yu-Cheng, Taichung, Taiwan, for a “method for erasing flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A block erase method for a flash memory is provided. The block erase method is to perform block erase on a block with a predetermined block size. The block erase method includes: performing an erase verification on bytes byte-by-byte in the block when performing the block erase; checking an erase step of the byte when the byte does not pass the erase verification; when the erase step of the byte exceeds a predetermined threshold value, performing the block erase with a partitioned block smaller than the predetermined block size, and returning to an erase verification stage to perform the erase verification; and when the erase step of the bytes does not exceed the predetermined threshold value, continuing to perform the block erase with the predetermined block size, and returning to the erasure verification stage to continue to perform the erase verification.”

The patent application was filed on 2022-12-01 (18/072723).

Semiconductor storage device and writing method
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (12198745) developed by Yano; Masaru, Kanagawa, Japan, for “semiconductor storage device and writing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device and its writing method are provided. A memory cell array is formed on a substrate, and the memory cell array has an NOR array with an NOR flash memory structure and a resistive random access array with a resistive random access memory (RRAM) structure. A read/write control unit charges a selected global bit line when a set write operation is performed on a selected memory cell of the resistive random access array, and a set write voltage is applied to the selected memory cell by applying a voltage charging the selected global bit line.”

The patent application was filed on 2022-05-04 (17/736995).

Semiconductor device and erasing method
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (12198768) developed by Yano; Masaru, Kanagawa, Japan, for “semiconductor device and erasing method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device and an erasing method may control a number of times an erase pulse. The erasing method of a flash memory includes the following. Multiple sacrificial memory cells in a block are programmed with different write levels first. When a selected block is erased in response to an erase command, a monitor erase pulse (R1) is applied to a well, and then the sacrificial memory cells are verified (S_EV). When the verification fails, a voltage of the monitor erase pulse is increased and then a monitor erase pulse (R2) is applied until the verification of the sacrificial memory cells passes. When the verification is passed, a normal erase pulse (Q1) is applied to the well based on a voltage of the monitor erase pulse (R2) to erase the selected block.”

The patent application was filed on 2022-03-16 (17/695852).

Semiconductor memory device and write method
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (12198758) developed by Aoki; Hajime, Yokohama, Japan, for “semiconductor memory device and write method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory device according to the present invention has a memory cell array, a write-driving/bias-reading circuit, a control circuit and a sense amplifier. The control circuit outputs a VSLC (Verify Sense Load Control) signal generated according to writing data. After the write-driving/bias-reading circuit applied the writing pulse and the complementary writing pulse, the sense amplifier receives the VSLC signal and detects the current difference between two currents respectively flowing through a first data line and a second data line; the first data line and the second data line respectively connecting a true memory cell and a complementary memory cell of the selected pair of memory cell. The control circuit controls to provide the additional current to at least one of the first data line and the second data line so as to make the detected current difference meet the required margin.”

The patent application was filed on 2022-12-07 (18/076991).

Memory device and method for manufacturing
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (12193224) developed by Li; Chun-Lin, Taichung, Taiwan, for “memory device and method for manufacturing the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a substrate and an eFuse structure. The substrate includes an array region and an eFuse region and the eFuse region of the substrate has an eFuse trench. The eFuse structure includes a first gate oxide layer, a plurality of doped regions, a dummy buried word line, and an eFuse gate electrode. The first gate oxide layer is conformally formed on a surface of the eFuse trench. The doped regions are respectively formed in the substrate on opposite sides outside the eFuse trench, and in contact with the first gate oxide layer. The dummy buried word line is formed on the first gate oxide layer. The eFuse gate electrode is formed on the dummy buried word line and in contact with the first gate oxide layer. The dummy buried word line is electrically isolated from the eFuse gate electrode.”

The patent application was filed on 2022-02-02 (17/591299).

Memory array having error checking and correction circuit
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (12190981) developed by Tsai; Yao-Ting, and Chuang; Che-Fu, Taichung, Taiwan, for “memory array having error checking and correction circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.”

The patent application was filed on 2022-07-18 (17/866558).

Semiconductor memory apparatus and testing method
Winbond Electronics Corp., Taichung, Taiwan, has been assigned a patent (12190980) developed by Liao; Shao-Ching, Wu; Chien-Min, and Hsieh; Kuang-Chih, Taichung, Taiwan, for “semiconductor memory apparatus and testing method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory apparatus and a testing method thereof are provided. The semiconductor memory apparatus includes a memory chip and a memory controller. The memory controller is configured to detect an initial test voltage of a target memory cell corresponding to a tailing bit in a main array of the memory chip. After the memory chip is idle for a first time, the memory controller detects a first test voltage of the target memory cell and compares it with a current comparison voltage to determine whether a first stage test is passed. In a case of passing the first stage test, after the memory chip is idle for a second time, the memory controller detects a second test voltage of the target memory cell and compares it with the current comparison voltage to determine whether a second stage test is passed. The comparison voltage is dynamically updated in response to the time the memory chip is idle.”

The patent application was filed on 2023-02-21 (18/171666).