NEO Semiconductor Assigned Patent

NEO Semiconductor, Inc., San Jose, CA, has been assigned a patent (12100460) developed by Hsu, Fu-Chang, San Jose, CA, for “methods and apparatus for NAND flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and apparatus for NAND flash memory are disclosed. In an embodiment, a method is provided for programming a NAND flash memory. The method includes precharging selected bit lines of selected memory cells with a bias voltage level while unselected bit lines maintain the inhibit voltage, applying a verify voltage to a selected word line that is coupled to the selected memory cells, and discharging the selected bit lines that are coupled to on-cells over a first time interval. The method also includes sensing a sensed voltage level on a selected bit line, loading the selected bit line with the inhibit voltage level when the sensed voltage level is above a threshold level and a program voltage when the sensed voltage level is equal to or below the threshold level, and repeating the operations of sensing and loading for each of the selected bit lines.”

The patent application was filed on 2021-05-25 (17/330304).