R&D: High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory, Observations, Analysis, and Modeling

IEEE Transactions on Computers has published an article written by Guangkuo Yang; School of Information Science and Engineering, Shandong University, Qingdao, China, Meng Zhang; School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, China, Peng Guo; Shandong Sinochip Semiconductors Co., Ltd, P. R. China, Xuepeng Zhan; School of Information Science and Engineering, Shandong University, Qingdao, China, and State Key Laboratory of High-End Server & Storage Technology, Jinan, China, Shaoqi Yang; Xiaohuan Zhao ; Xinyi Guo ; Pengpeng Sang, Jixuan Wu, School of Information Science and Engineering, Shandong University, Qingdao, China, Fei Wu, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, China, and Jiezhi Chen, School of Information Science and Engineering, Shandong University, Qingdao, China.

Abstract: “In the age of artificial intelligence, large language models (LLM) require rapid development along with massive volumes of training data and parameter storage. Over the past decade, 3D NAND flash memory has emerged as the dominant non-volatile memory technology due to its high bit density and large capacity. However, because of its 3D vertical stacking technique and array designs, 3D NAND flash memory has more complicated data loss mechanisms compared to 2D NAND flash memory. As bit densities rise to Quad-level-cells (QLC), the small read margins will further complicate and make the situation more unpredictable. In this work, we propose an error-bit prediction model in this paper for 3D QLC NAND flash memory with the charge-trap (CT) cell structure based on a thorough analysis of multiple parameters that affect the error-bit distributions, including read disturb (RD) and degradation from program/erase (PE) cycles. Specifically, we develop the whole-block prediction (WBP) and the dynamic-worst-page prediction (DWPM) models. It is shown that the proposed models can be used for high-precision error-bit prediction to guarantee data reliability in commonly used NAND-based storage systems based on the characterization results of raw NAND chips.“