Alphawave Semi Introduces 64Gb Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP Subsystem

Alphawave Semi introduces an industry’s first 64Gb Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP Subsystem to deliver chiplet interconnect data rates, setting a new standard for ultra-high-performance D2D connectivity solutions in the industry.

The 3rd Gen, 64Gb IP Subsystem builds on the successes of the most recent Gen2 36Gb IP subsystem and silicon-proven Gen1 24Gb and is available in TSMC’s 3nm Technology for both Standard and Advanced packaging. The silicon proven success and tapeout milestones pave the way for Alphawave Semi’s Gen3 UCIe IP subsystem offering.

The company is set to revolutionize connectivity with its Gen3 64Gb UCIe IP, delivering a bandwidth density of over 20Tbps/mm, with ultra-low power and latency. This solution is highly configurable supporting multiple protocols, including AXI-4, AXI-S, CXS, CHI and CHI-C2C to address the growing demands for high-performance connectivity across disaggregated systems in HPC, data centers, and AI applications.

The design complies with the latest UCIe Specification and has a scalable architecture with features for advanced testability, including live per-lane health monitoring, making it a robust foundation and enabling an open and interoperable chiplet ecosystem.

UCIe D2D interconnects facilitate a range of standard and emerging chiplet connectivity scenarios. Common uses encompass linking compute chiplets for a low-latency, coherent connection via UCIe’s streaming capabilities, as well as connecting compute to I/O chiplets using UCIe interfaces with PCIe, CXL, or Ethernet. Additionally, optical retimers can leverage the UCIe chiplet architecture to establish dependable, low-latency optical I/O links through optical engines, enhancing off-system connectivity. This supports the development of low-power, high-speed solutions in data centers and AI/ML systems.

For high performance applications, creating a custom HBM base die using the latest UCIe standard is a cutting-edge approach that involves tightly integrating memory dies with compute dies to achieve extremely high bandwidth as well as a low latency between the components. This allows for reuse of die-to-die shoreline already occupied on the main die for core-to-core or core-to-I/O connections. This approach greatly optimizes memory transactions in AI applications where low power and reduced latency are performance differentiators.

“UCIe Consortium is delighted to see members achieving critical milestones like tapeouts, which demonstrate the growing adoption of the UCIe Specification,” said Brian Rea, marketing work group chair, UCIe Consortium. “UCIe is a cornerstone of the chiplet industry, providing a robust solution for high-speed, low-latency die-to-die interconnects. By embracing open standards, we’re empowering the industry to accelerate innovation, reduce time-to-market, and deliver groundbreaking technologies.”

“Our successful tapeout of the Gen2 UCIe IP at 36 Gbps on 3nm technology builds on our pioneering silicon-proven 3nm UCIe IP with CoWoS packaging,” said Mohit Gupta, Senior VP and GM, custom silicon and IP, Alphawave Semi. “This achievement sets the stage for our Gen3 UCIe IP at 64Gb, which is on target to deliver high performance, 20 Tbps/mm throughput functionality to our customers who need the maximization of shoreline density for critical AI bandwidth needs in 2025.”

This achievement, alongside Alphawave Semi’s earlier industry-first 3nm silicon-proven Gen1 UCIe IP, reaffirms the company’s rapid progress as a leader in high-performance chiplet connectivity solutions with full suite of silicon-proven connectivity IP subsystems tailored for hyperscaler and data-infrastructure markets.

Resources:
Alphawave Semi’s UCIe IP solutions
Press release on the industry’s first silicon-proven 3nm UCIe IP   
Explore multi-protocol chiplet press release              
Watch DAC 2024 video: From Simulation to Silicon: Alphawave and Keysight’s UCIe Validation.   
Blog: Redefining XPU Memory for AI Data Centers Through Custom HBM.