R&D: Characterizing and Optimizing Low-Density Parity Check (LDPC) Performance on 3D NAND Flash Memories

ACM Transactions on Architecture and Code Optimization (TACO) has published an article written by Qiao Li, Yu Chen, School of Informatics, Xiamen University, Xiamen, China, Guanyu Wu, Xiamen University, Xiamen, China, Yajuan Du, School of Computer Science and Technolog, Wuhan University of Technology, Wuhan, China, Min Ye, Department of Computer Science, City University of Hong Kong, Hong Kong, Hong Kong, Xinbiao Gan, National University of Defense Technology, Changsha, China, jie zhang, The school of Computer Science, Peking University, Beijing, China, Zhirong Shen, Xiamen University, xiamen, China, Jiwu Shu, Xiamen University, Xiamen, China, and Chun Xue, Computer Science, City University of Hong Kong, Hong Kong, Hong Kong.

Abstract: “With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory. However, when the RBER is prohibitively high, LDPC decoding would introduce long latency. To study how LDPC performs on the latest 3D NAND flash memory, we conduct a comprehensive analysis of LDPC decoding performance using both the theoretically derived threshold voltage distribution model obtained through modeling (Modeling-based method) and the actual voltage distribution collected from on-chip data through testing (Ideal case). Based on LDPC decoding results under various interference conditions, we summarize four findings that can help us gain a better understanding of the characteristics of LDPC decoding in 3D NAND flash memory. Following our characterization, we identify the differences in LDPC decoding performance between the Modeling-based method and the Ideal case. Due to the accuracy of initial probability information, the threshold voltage distribution derived through modeling deviates by certain degrees from the actual threshold voltage distribution. This leads to a performance gap between using the threshold voltage distribution derived from the Modeling-based method and the actual distribution. By observing the abnormal behaviors in the decoding with the Modeling-based method, we introduce an Offsetted Read Voltage (ΔRV) method, for optimizing LDPC decoding performance by offsetting the reading voltage in each layer of a flash block. The evaluation results show that our ΔRV method enhances the decoding performance of LDPC on the Modeling-based method by reducing the total number of sensing levels needed for LDPC decoding by 0.67% to 18.92% for different interference conditions on average, under the P/E cycles from 3000 to 7000.“