Monolithic 3D Assigned Two Patents

3D memory devices and structures with memory arrays and metal layers
Monolithic 3D Inc., Klamath Falls, OR, has been assigned a patent (12041791) developed by Or-Bach; Zvi, Haifa, Israel, Han; Jin-Woo, San Jose, CA, and Cronquist; Brian, Klamath Falls, OR, for a “3D memory devices and structures with memory arrays and metal layers.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor device including: a first level including a plurality of first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; and a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes (FFHs), where the second level includes second filled holes (SFHs), where the SFHs are aligned to the FFHs with a more than 1 nm but less than 40 nm alignment error, where the third level includes a plurality of Look-Up-Table circuits.”

The patent application was filed on 2024-02-02 (18/431177).

3D memory semiconductor devices and structures with memory cells preliminary class
Monolithic 3D Inc., Klamath Falls, OR, has been assigned a patent (12041792) developed by Or-Bach; Zvi, Haifa, Israel, Han; Jin-Woo, San Jose, CA, and Lusky; Eli, Ramat-Gan, Israel, for a “3D memory semiconductor devices and structures with memory cells preliminary class.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.”

The patent application was filed on 2024-03-14 (18/605401).