InnoGrit Assigned Two Patents
ECC architecture with memory mapping, hybrid PCB topology and layout with clamshell placement for storage applications
By Francis Pelletier | August 23, 2024 at 2:00 pmECC architecture with memory mapping
InnoGrit Technologies Co., Ltd., Shanghai, China, has been assigned a patent (12032441) developed by Zhu; Xiaoming, San Jose, CA, Chen; Jie, Milpitas, CA, Fu; Bo, Cupertino, CA, and Wu; Zining, Los Altos, CA, for “systems and methods for an ECC architecture with memory mapping.”
The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, apparatus and methods are provided for providing an error correction code (ECC) architecture with flexible memory mapping. An apparatus may include an error correction code (ECC) engine, a multi-channel interface for one or more non-volatile storage devices, a memory including a plurality of memory units, a storage containing a plurality of mapping entries to indicate allocation status of the plurality of memory units and a memory mapping manager. The plurality of memory units may be coupled to the ECC engine and the multi-channel interface. The memory mapping manager may be configured to control allocation of the plurality of memory units and set allocation status in the plurality of mapping entries.”
The patent application was filed on 2023-06-30 (18/216628).
Hybrid PCB topology and layout with clamshell placement for storage applications
InnoGrit Technologies Co., Ltd., Shanghai, China, has been assigned a patent (12032499) developed by Zhao; Gang, Chandler, AZ, and Chen; Lin, Cupertino, CA, for “Hybrid PCB topology and layout with clamshell placement for storage applications.”
The abstract of the patent published by the U.S. Patent and Trademark Office states: “A hybrid printed circuit board (PCB) topology is provided. A non-volatile storage system may include a PCB, a first non-volatile storage device attached to a first side of the PCB, a second non-volatile storage device attached to a second side of the PCB, and a storage controller coupled to the first and second non-volatile storage devices by a shared channel. The two devices may be placed in a clamshell configuration but have different capacities. The shared channel may have a first signal route to a first pin of the first non-volatile storage device and a second signal route to a second pin of the second non-volatile storage device. The first pin may have a pin capacitance that is smaller than that of the second pin. The first signal route has an extra resistor in series compared to the second signal route.”
The patent application was filed on 2022-07-11 (17/861325).
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