JEDEC Near Finalization of HBM4 Standard, Eyes Future Innovations
HBM4 aims to further enhance data processing rates while maintaining essential features such as higher bandwidth, lower power consumption, and increased capacity per die and/or stack.
This is a Press Release edited by StorageNewsletter.com on July 17, 2024 at 2:18 pmJEDEC Solid State Technology Association announced it is nearing completion of the next version of its anticipated High Bandwidth Memory (HBM) DRAM standard: HBM4.
Designed as an evolutionary step beyond the currently published HBM3 standard, HBM4 aims to further enhance data processing rates while maintaining essential features such as higher bandwidth, lower power consumption, and increased capacity per die and/or stack.
These advancements are vital for applications that require efficient handling of large datasets and complex calculations, including GenAI, HPC, high-end graphics cards, and servers.
HBM4 is set to introduce a doubled channel count per stack compared to HBM3, with a larger physical footprint. To support device compatibility, the standard ensures that a single controller can work with both HBM3 and HBM4 if needed. Different configurations will require various interposers to accommodate the differing footprints. HBM4 will specify 24 and 32Gb layers, with options for supporting 4-high, 8-high, 12-high and 16-high TSV stacks. The committee has initial agreement on speeds bins up to 6.4Gb/s with discussion ongoing for higher frequencies.
JEDEC encourages companies to join and help shape the future of JEDEC standards. Membership grants access to pre-publication proposals and provides early insights into active projects like HBM4.
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Discover the benefits of membership and join today.
JEDEC standards are subject to change during and after the development process, including disapproval by the JEDEC board of directors.
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