Phison Electronics Assigned Nineteen Patents

Data rebuilding method, memory storage apparatus, and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11983069) developed by Yan; Horng-Sheng, Penghu County, Taiwan, for “data rebuilding method, memory storage apparatus, and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data rebuilding method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: establishing a connection between the memory storage apparatus and a host system; storing a first data to a memory of the host system via the connection; detecting an error in the first data in the memory; and rebuilding a part of data in the first data in the memory according to the error.”

The patent application was filed on 2021-07-28 (17/386547).

Data retry-read method, memory storage device, and memory control circuit element
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11977745) developed by Tseng; Ming-Hui, Hsinchu, Taiwan, Ma; Chia-Lung, New Taipei, Taiwan, and Weng; Zhen-Yu, Taoyuan, Taiwan, for “data retry-read method, memory storage device, and memory control circuit element.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.”

The patent application was filed on 2022-08-11 (17/886416).

Read voltage level correction method, memory storage device, and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11972139) developed by Zeng; Shih-Jia, Hsinchu, Taiwan, Tsao; Chun-Wei, Taoyuan, Taiwan, Lin; Hsiao-Yi, Yilan County, Taiwan, and Lin; Wei, Taipei, Taiwan, for “read voltage level correction method, memory storage device, and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.”

The patent application was filed on 2022-02-24 (17/679109).

Memory control method, memory storage device and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11960761) developed by Hu; Chun-Yang, Miaoli County, Taiwan, and Hung; Yi-Tein, Pingtung County, Taiwan, for “memory control method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory control method is disclosed according to an embodiment. The method includes: temporarily storing first type data into a buffer memory, wherein the first type data is preset to be stored into a rewritable non-volatile memory module based on a first programming mode; in a state that the first type data is stored in the buffer memory, temporarily storing second type data into the buffer memory, and the second type data is preset to be stored into the rewritable non-volatile memory module based on a second programming mode different from the first programming mode; and in a state that a data volume of the first type data in the buffer memory does not reach a first threshold, if a data volume of the second type data in the buffer memory reaches a second threshold, storing the first type data in the buffer memory into the rewritable non-volatile memory module.”

The patent application was filed on 2020-12-11 (17/118605).

Memory check method, memory check device, and memory check system
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11960381) developed by Tseng; Chien Chang, Miaoli County, Taiwan, for “memory check method, memory check device, and memory check system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory check method, a memory check device and a memory check system are disclosed. The method includes the following. A debug file is generated according to a source code, where the debug file carries symbol information related to a description message in the source code. Memory data generated by a memory storage device in execution of a firmware is received. The debug file is loaded to automatically analyze the memory data. In addition, an analysis result is presented by an application program interface, where the analysis result reflects a status of the firmware with assistance of the symbol information.”

The patent application was filed on 2021-03-15 (17/200910).

Managing memory buffer and memory control circuit unit and memory storage apparatus
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11960762) developed by Hsiao; Po-Wen, Taipei, Taiwan, and Lin; Chun Hao, Taoyuan, Taiwan, for “method for managing memory buffer and memory control circuit unit and memory storage apparatus thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method for managing a memory buffer, a memory control circuit unit, and a memory storage apparatus are provided. The method includes the following steps. Multiple consecutive first commands are received from a host system. A command ratio of read command among the first commands is calculated. The memory storage apparatus is being configured in a first mode or a second mode according to the command ratio and a ratio threshold. A first buffer is configured in a buffer memory to temporarily store a logical-to-physical address mapping table in response to the memory storage device being configured in the first mode, in which the first buffer has a first capacity. A second buffer is configured in the buffer memory in response to the memory storage device being configured in the second mode, in which the second buffer has a second capacity, which is greater than the first capacity.”

The patent application was filed on 2021-08-12 (17/400131).

Decoding method, memory storage device and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11962328) developed by Zeng; Shih-Jia, Hsinchu, Taiwan, Chang; Yi-Fang, Tsao; Chun-Wei, Taoyuan, Taiwan, Hsu; Chen-An, New Taipei, Taiwan, and Lin; Wei, Taipei, Taiwan, for “decoding method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.”

The patent application was filed on 2022-11-28 (17/994399).

Memory management method, memory storage device and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11954329) developed by Yeh; Chih-Kang, Kinmen County, Taiwan, for “memory management method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.”

The patent application was filed on 2022-04-15 (17/721358).

Command management method, memory storage device and memory control circuit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11928358) developed by Tseng; Ming-Hui, Hsinchu, Taiwan, for “command management method, memory storage device and memory control circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A command management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: obtaining a plurality of commands from a memory of a host system; storing the commands in a first buffer region of the memory storage device; in response to a first command and a second command meeting a pairing condition in the first buffer region, putting the first command and the second command in the first buffer region in a first command queue of the memory storage device; and continuously executing the first command and the second command in the first command queue.”

The patent application was filed on 2022-02-16 (17/672685).

Memory management method, memory storage device, and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11907529) developed by Huang; Sheng-Min, Hsinchu County, Taiwan, Ho; Kuo-Hwa, Miaoli, Taiwan, and Song; Shih-Ying, New Taipei, Taiwan, for “memory management method, memory storage device, and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: obtaining a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed; obtaining a second weight value corresponding to at least one second command being executed; and in response to a sum of the first weight value and the second weight value being greater than a base value, delaying an execution of the first command.”

The patent application was filed on 2022-02-15 (17/671597).

Abnormal power loss recovery method, memory control circuit unit, and memory storage device
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11907059) developed by Tan; Kok-Yong, Miaoli County, Taiwan, for “abnormal power loss recovery method, memory control circuit unit, and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.”

The patent application was filed on 2022-04-07 (17/715050).

Signal re-driving device, data storage system and mode control method
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11886263) developed by Chou; Po-Jung, Taipei, Taiwan, Chen; Sheng-Wen, Hsinchu County, Taiwan, and Chen; Chung-Kuang, Nantou County, Taiwan, for “signal re-driving device, data storage system and mode control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A signal re-driving device, a data storage system and a mode control method are provided. The method includes the following steps. A first signal is received via a receiving circuit of the signal re-driving device. An analog signal feature is detected the receiving circuit. A first mode is entered according to the analog signal feature. The first signal is modulated and a second signal is outputted in the first mode. The second signal is sent via a sending circuit of the signal re-driving device. A digital signal feature is detected via the receiving circuit. And, the first mode is switched to a second mode according to the digital signal feature.”

The patent application was filed on 2021-08-27 (17/458548).

Encoding control method, memory storage device and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11853613) developed by Lin; Yu-Hsiang, Yunlin County, Taiwan, and Huang; Bo Lun, Tainan, Taiwan, for “encoding control method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.”

The patent application was filed on 2022-04-20 (17/724504).

Switching power supply module and memory storage device
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11843311) developed by Chou; Shu-Han, New Taipei, Taiwan, for “switching power supply module and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A switching power supply module and a memory storage device are disclosed. The switching power supply module includes a first voltage regulation circuit, a second voltage regulation circuit, a switch circuit and a control circuit. The first voltage regulation circuit is configured to regulate an original power as a first power. The second voltage regulation circuit is configured to regulate the original power as a second power. The control circuit is configured to control the switch circuit to conduct a first power supply path under a first status to provide the first power to the first power supply target. The control circuit is further configured to control the switch circuit to conduct a second power supply path under a second status to provide the second power to the second power supply target.”

The patent application was filed on 2021-12-03 (17/541251).

Memory control method, memory storage device, and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11829644) developed by Su; Po-Cheng, Hsinchu, Taiwan, Wang; Chih-Wei, Tainan, Taiwan, Hsu; Yu-Cheng, Yilan County, Taiwan, and Lin; Wei, Taipei, Taiwan, for “memory control method, memory storage device, and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.”

The patent application was filed on 2022-01-22 (17/581858).

Data writing method based on different numbers of chip enabled regions, memory storage device and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11816355) developed by Yeh; Chih-Kang, Kinmen County, Taiwan, for “data writing method based on different numbers of chip enabled regions, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes receiving first data from a host system; sending a first write command sequence instructing continuous writing of the first data to a plurality of first chip enabled (CE) regions in response to the memory storage device being in a first state; receiving second data from the host system; and sending a second write command sequence instructing continuous writing of the second data to at least one second CE region in response to the memory storage device being in a second state. A data amount of the first data is equal to a data amount of the second data. A total number of the first CE regions is greater than a total number of the at least one second CE region.”

The patent application was filed on 2021-03-25 (17/213152).

Memory management method, memory storage device, and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11809706) developed by Yang; Yu-Siang, New Taipei, Taiwan, Hsu; Yu-Cheng, Yilan County, Taiwan, Kuo; Tsai-Hao, Tainan, Taiwan, Lin; Wei, and Liu; An-Cheng, Taipei, Taiwan, for “memory management method, memory storage device, and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.”

The patent application was filed on 2021-06-17 (17/349918).

Read disturb checking method, memory storage device and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11797222) developed by Zeng; Shih-Jia, Su; Po-Cheng, Hsinchu, Taiwan, Wang; Chih-Wei, Tainan, Taiwan, and Lin; Wei, Taipei, Taiwan, for “read disturb checking method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.”

The patent application was filed on 2022-01-17 (17/577012).

Data merging method, memory storage device for updating copied L2P mapping table according to physical address of physical unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (11755242) developed by Kuo; Che-Yueh, New Taipei, Taiwan, and Lien; Li Hsun, Taichung, Taiwan, for “data merging method, memory storage device for updating copied L2P mapping table according to the physical address of physical unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data merging method can copy a new logical to physical mapping table and update a copied logical to physical mapping table according to a physical address of a recycling unit expected to be written at the same time. In this way, the number of times that the same logic to physical mapping table is read multiple times during the data merging operation can be reduced to improve the execution efficiency of the data merging operation, thereby increasing the system performance of the memory storage device.”

The patent application was filed on 2020-08-10 (16/988731).