Kepler Computing Assigned Eleven Patents

Ferroelectric memory devices
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11871583) developed by Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Mukherjee, Niloy, San Ramon, CA, Mathuriya, Amrita, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, and Manipatruni, Sasikanth, Portland, OR, for “ferroelectric memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.”

The patent application was filed on 2021-09-17 (17/478849).

Ferroelectric memory device integrated with transition electrode
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11854593) developed by Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Mukherjee, Niloy, San Ramon, CA, Mathuriya, Amrita, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, and Manipatruni, Sasikanth, Portland, OR, for a “ferroelectric memory device integrated with a transition electrode.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.”

The patent application was filed on 2021-09-17 (17/478850).

Ferroelectric memory chiplet as unified memory in multi-dimensional packaging
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11844223) developed by Mathuriya, Amrita, Wilkerson, Christopher B., Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Olaosebikan, Debo, San Francisco, CA, and Manipatruni, Sasikanth, Portland, OR, for a “ferroelectric memory chiplet as unified memory in a multi-dimensional packaging.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.”

The patent application was filed on 2021-04-13 (17/229750).

Integrated via and bridge electrodes for memory array applications and methods of fabrication
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11839088) developed by Sato, Noriyuki, Hillsboro, OR, Mukherjee, Niloy, San Ramon, CA, Manfrini, Mauricio, Heverlee, Belgium, Gosavi, Tanay, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Rathi, Somilkumar J., San Jose, CA, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for “integrated via and bridge electrodes for memory array applications and methods of fabrication.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.”

The patent application was filed on 2021-12-16 (17/553508).

Multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11837268) developed by Dokania, Rajeev Kumar, Beaverton, OR, Mathuriya, Amrita, Portland, OR, Olaosebikan, Debo, San Francisco, CA, Gosavi, Tanay, Portland, OR, Sato, Noriyuki, Hillsboro, OR, and Manipatruni, Sasikanth, Portland, OR, for a “multi-element ferroelectric gain memory bit-cell having stacked and folded planar capacitors with lateral offset.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.”

The patent application was filed on 2022-03-11 (17/654560).

High density FeRAM devices and methods of fabrication
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11832451) developed by Guhabiswas, Debraj, Berkeley, CA, Perez, Maria Isabel, San Francisco, CA, Wu, Jason Y., Albany, CA, Clarkson, James David, El Sobrante, CA, Velarde, Gabriel Antonio Paulius, San Leandro, CA, Mukherjee, Niloy, San Ramon, CA, Sato, Noriyuki, Hillsboro, OR, Mathuriya, Amrita, Manipatruni, Sasikanth, Portland, OR, and Ramesh, Ramamoorthy, Moraga, CA, for “high density ferroelectric random access memory (FeRAM) devices and methods of fabrication.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.”

The patent application was filed on 2021-08-06 (17/396609).

Rapid Thermal Annealing (RTA) methodologies for integration of perovskite-material based trench capacitors
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11769790) developed by Mukherjee, Niloy, San Ramon, CA, Rathi, Somilkumar J., San Jose, CA, Wu, Jason Y., Albany, CA, Pandey, Pratyush, Kensington, CA, Ren, Zeying, Albany, CA, Atiquzzaman, Fnu, Orinda, CA, Velarde, Gabriel Antonio Paulius, San Leandro, CA, Sato, Noriyuki, Hillsboro, OR, Manfrini, Mauricio, Heverlee, Belgium, Gosavi, Tanay, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Mathuriya, Amrita, Portland, OR, Ramesh, Ramamoorthy, Moraga, CA, and Manipatruni, Sasikanth, Portland, OR, for “Rapid Thermal Annealing (RTA) methodologies for integration of perovskite-material based trench capacitors.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.”

The patent application was filed on 2022-02-01 (17/649665).

Endurance of NVM banks via multi-level wear leveling
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11823725) developed by Wilkerson, Christopher B., Manipatruni, Sasikanth, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, and Mathuriya, Amrita, Portland, OR, for “apparatus and method for endurance of non-volatile memory banks via multi-level wear leveling.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.”

The patent application was filed on 2021-06-25 (17/359295).

The patent application was filed on 2022-02-01 (17/649665).

Process integration flow for embedded memory enabled by decoupling processing of memory area from non-memory area
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11765909) developed by Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Mukherjee, Niloy, San Ramon, CA, Dokania, Rajeev Kumar, Beaverton, OR, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for a “process integration flow for embedded memory enabled by decoupling processing of a memory area from a non-memory area.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.”

The patent application was filed on 2021-06-11 (17/345964).

Memory device fabrication through wafer bonding
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11765908) developed by Manfrini, Mauricio, Heverlee, Belgium, Sato, Noriyuki, Hillsboro, OR, Clarkson, James David, El Sobrante, CA, Fernandez, Abel, Berkeley, CA, Rathi, Somilkumar J., San Jose, CA, Mukherjee, Niloy, San Ramon, CA, Gosavi, Tanay, Mathuriya, Amrita, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, and Manipatruni, Sasikanth, Portland, OR, for a “memory device fabrication through wafer bonding.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.”

The patent application was filed on 2023-02-10 (18/167816).