Sunrise Memory Assigned Eight Patents

Fabricating 3D memory structure of NOR memory strings
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11751391) developed by Purayath; Vinod, Sedona, AZ, Nosho; Yosuke, Tokyo, Japan, Kamisaka; Shohei, Kanagawa, Japan, Nakane; Michiru, Tokyo, Japan, and Harari; Eli, Saratoga, CA, for “methods for fabricating a 3-dimensional memory structure of NOR memory strings.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.”

The patent application was filed on 2021-07-21 (17/382126).

Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of memory cell in a 3D NOR memory string array
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11705496) developed by Chien; Wu-Yi Henry, San Jose, CA, Herner; Scott Brad, Portland, OR, and Harari; Eli, Saratoga, CA, for a “charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional NOR memory string array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO.sub.2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.”

The patent application was filed on 2021-04-05 (17/222082).

High capacity memory circuit with low effective latency
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11675500) developed by Kim; Youn Cheul, Saratoga, CA, Chernicoff; Richard S., Mercer Island, WA, Quader; Khandker Nazrul, Santa Clara, CA, Norman; Robert D., Pendleton, OR, Yan; Tianhong, Saratoga, CA, Salahuddin; Sayeef, Walnut Creek, CA, and Harari; Eli, Saratoga, CA, for a “high capacity memory circuit with low effective latency.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.”

The patent application was filed on 2021-02-05 (17/169387).

Device with embedded high-bandwidth, high-capacity memory using wafer bonding
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11670620) developed by Quader; Khandker Nazrul, Santa Clara, CA, Norman; Robert, Pendleton, OR, Lee; Frank Sai-keung, San Jose, CA, Petti; Christopher J., Mountain View, CA, Herner; Scott Brad, Lafayette, CO, Chan; Siu Lung, San Jose, CA, Salahuddin; Sayeef, Walnut Creek, CA, Mofidi; Mehrdad, Los Altos Hills, CA, and Harari; Eli, Saratoga, CA, for a “device with embedded high-bandwidth, high-capacity memory using wafer bonding.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.”

The patent application was filed on 2020-01-29 (16/776279).

Processes for forming 3D horizontal NOR memory arrays
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11610909) developed by Harari; Eli, Saratoga, CA, and Chien; Wu-Yi Henry, San Jose, CA, for “processes for forming 3-dimensional horizontal NOR memory arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A process forms thin-film storage transistors (e.g., HNOR devices) with improved channel regions by conformally depositing a thin channel layer in a cavity bordering a source region and a drain region, such that a portion of the channel material abuts by junction contact the source region and another portion of the channel layer abut by junction contact the drain region. The cavity is also bordered by a storage layer. In one form of the process, the channel region is formed before the storage layer is formed. In another form of the storage layer is formed before the channel region is formed.”

The patent application was filed on 2020-05-15 (16/875460).

Vertical thin-film transistor and application as bit-line connector for 3D memory arrays
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11610914) developed by Yan; Tianhong, Saratoga, CA, Herner; Scott Brad, Portland, OR, Zhou; Jie, San Jose, CA, Chien; Wu-Yi Henry, San Jose, CA, and Harari; Eli, Saratoga, CA, for “vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.”

The patent application was filed on 2021-01-28 (17/161504).

Quasi-volatile system-level memory
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11580038) developed by Norman; Robert D., Pendleton, OR, Harari; Eli, Saratoga, CA, Quader; Khandker Nazrul, Santa Clara, CA, Lee; Frank Sai-keung, San Jose, CA, Chernicoff; Richard S., Mercer Island, WA, Kim; Youn Cheul, Saratoga, CA, and Mofidi; Mehrdad, Los Altos Hills, CA, for a “quasi-volatile system-level memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.”

The patent application was filed on 2021-02-05 (17/169212).

Channel controller for shared memory access
Sunrise Memory Corporation, San Jose, CA, has been assigned a patent (11561911) developed by Norman; Robert D., Pendleton, OR, Chernicoff; Richard S., Mercer Island, WA, and Harari; Eli, Saratoga, CA, for a “channel controller for shared memory access.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.”

The patent application was filed on 2021-02-23 (17/183154).