Kepler Computing Assigned Twenty-Three Patents

High-density low voltage ferroelectric memory bit-cell
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11527277) developed by Dokania, Rajeev Kumar, Beaverton, OR, Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Pandey, Pratyush, Oakland, CA, Olaosebikan, Debo, San Francisco, CA, Mathuriya, Amrita, Manipatruni, Sasikanth, Portland, OR, for a “high-density low voltage ferroelectric memory bit-cell.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization by applying different voltage levels or different time pulse widths at the same voltage level.”

The patent application was filed on 2021-06-04 (17/339850).

Non-linear polar material based memory bit-cell with multi-level storage by applying different time pulse widths
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11527278) developed by Dokania, Rajeev Kumar, Beaverton, OR, Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Pandey, Pratyush, Kensington, CA, Olaosebikan, Debo, San Francisco, CA, Mathuriya, Amrita, Manipatruni, Sasikanth, Portland, OR, for a “non-linear polar material based memory bit-cell with multi-level storage by applying different time pulse widths.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization by applying different voltage levels or different time pulse widths at the same voltage level.”

The patent application was filed on 2021-07-02 (17/367101).

Stacked ferroelectric planar capacitors in memory bit-cell
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11521667) developed by Dokania, Rajeev Kumar, Beaverton, OR, Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Pandey, Pratyush, Kensington, CA, Olaosebikan, Debo, San Francisco, CA, Mathuriya, Amrita, Manipatruni, Sasikanth, Portland, OR, for a “stacked ferroelectric planar capacitors in a memory bit-cell.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization by applying different voltage levels or different time pulse widths at the same voltage level.”

The patent application was filed on 2021-06-25 (17/359325).

High-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11521666) developed by Dokania, Rajeev Kumar, Beaverton, OR, Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Pandey, Pratyush, Kensington, CA, Olaosebikan, Debo, San Francisco, CA, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for a “high-density low voltage multi-element ferroelectric gain memory bit-cell with planar capacitors.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization by applying different voltage levels or different time pulse widths at the same voltage level.”

The patent application was filed on 2021-06-11 (17/346087).

3D stacked ferroelectric compute and memory
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11521953) developed by Manipatruni, Sasikanth, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Mathuriya, Amrita, Portland, OR, and Ramesh, Ramamoorthy, Moraga, CA, for “3D stacked ferroelectric compute and memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate, a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.”

The patent application was filed on 2021-07-30 (17/390799).

Pulsing scheme for ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11521668) developed by Dokania, Rajeev Kumar, Beaverton, OR, Mathuriya, Amrita, Portland, OR, and Manipatruni, Sasikanth, Portland, OR, for a “pulsing scheme for a ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.”

The patent application was filed on 2021-11-18 (17/530360).

Ferroelectric capacitor integrated with logic
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11522044) developed by Thareja, Gaurav, Santa Clara, CA, Manipatruni, Sasikanth, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Ramesh, Ramamoorthy, Moraga, CA, and Mathuriya, Amrita, Portland, OR, for a “ferroelectric capacitor integrated with logic.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.”

The patent application was filed on 2020-02-19 (16/795404).

Non-linear polar material based differential multi-memory element gain bit-cell
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11514967) developed by Dokania, Rajeev Kumar, Beaverton, OR, Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Pandey, Pratyush, Kensington, CA, Olaosebikan, Debo, San Francisco, CA, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for a “non-linear polar material based differential multi-memory element gain bit-cell.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization by applying different voltage levels or different time pulse widths at the same voltage level.”

The patent application was filed on 2021-07-02 (17/367217).

Non-linear polar material based multi-memory element bit-cell with multi-level storage
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11514966) developed by Dokania, Rajeev Kumar, Beaverton, OR, Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Pandey, Pratyush, Oakland, CA, Olaosebikan, Debo, San Francisco, CA, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for a “non-linear polar material based multi-memory element bit-cell with multi-level storage.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization by applying different voltage levels or different time pulse widths at the same voltage level.”

The patent application was filed on 2021-07-02 (17/367172).

Sequential circuit without feedback or memory element
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11509308) developed by Mathuriya, Amrita, Portland, OR, Odinaka, Ikenna, Durham, NC, Dokania, Rajeev Kumar, Beaverton, OR, Rios, Rafael, Austin, TX, and Manipatruni, Sasikanth, Portland, OR, for a “sequential circuit without feedback or memory element.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.”

The patent application was filed on 2021-08-20 (17/407909).

Method of forming stacked ferroelectric non-planar capacitors in memory bit-cell
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11501813) developed by Dokania, Rajeev Kumar, Beaverton, OR, Sato, Noriyuki, Hillsboro, OR, Gosavi, Tanay, Portland, OR, Pandey, Pratyush, Kensington, CA, Olaosebikan, Debo, San Francisco, CA, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for a “method of forming stacked ferroelectric non-planar capacitors in a memory bit-cell.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization by applying different voltage levels or different time pulse widths at the same voltage level.”

The patent application was filed on 2021-07-30 (17/390791).

Method for using and forming low power ferroelectric based majority logic gate adder
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11502691) developed by Manipatruni, Sasikanth, Portland, OR, Fang, Yuan-Sheng, San Francisco, CA, Menezes, Robert, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Thareja, Gaurav, Santa Clara, CA, Ramesh, Ramamoorthy, Moraga, CA, and Mathuriya, Amrita, Portland, OR, for a “method for using and forming low power ferroelectric based majority logic gate adder.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.”

The patent application was filed on 2021-02-23 (17/183181).

Vectored sequential circuit with ferroelectric or paraelectric material
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11482990) developed by Mathuriya, Amrita, Portland, OR, Odinaka, Ikenna, Durham, NC, Dokania, Rajeev Kumar, Beaverton, OR, Rios, Rafael, Austin, TX, and Manipatruni, Sasikanth, Portland, OR, for a “vectored sequential circuit with ferroelectric or paraelectric material.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.”

The patent application was filed on 2021-08-20 (17/408053).

Pulsing scheme for ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11482270) developed by Dokania, Rajeev Kumar, Beaverton, OR, Mathuriya, Amrita, and Manipatruni, Sasikanth, Portland, OR, for a “pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.”

The patent application was filed on 2021-11-17 (17/529258).

High-density low voltage NVM with unidirectional plate-line and bit-line and pillar capacitor
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11482529) developed by Manipatruni, Sasikanth, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, and Ramesh, Ramamoorthy, Moraga, CA, for a “high-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.”

The patent application was filed on 2019-02-27 (16/288004).

Pillar capacitor and method of fabricating such
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11482528) developed by Thareja, Gaurav, Santa Clara, CA, Manipatruni, Sasikanth, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Ramesh, Ramamoorthy, Moraga, CA, and Mathuriya, Amrita, Portland, OR, for “pillar capacitor and method of fabricating such.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.”

The patent application was filed on 2019-12-27 (16/729278).

High-density low voltage NVM with unidirectional plate-line and bit-line and pillar capacitor
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11476260) developed by Manipatruni, Sasikanth, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, and Ramesh, Ramamoorthy, Moraga, CA, for “high-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.”

The patent application was filed on 2019-02-27 (16/287953).

High-density low voltage NVM with unidirectional plate-line and bit-line and pillar capacitor
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11476261) developed by Manipatruni, Sasikanth, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, and Ramesh, Ramamoorthy, Moraga, CA, for “high-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.”

The patent application was filed on 2019-02-27 (16/288006).

Doped polar layers and semiconductor device incorporating same
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11469327) developed by Ramamoorthy, Ramesh, Moraga, CA, Manipatruni, Sasikanth, Portland, OR, and Thareja, Gaurav, Santa Clara, CA, for “doped polar layers and semiconductor device incorporating same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor, which in turn comprises a polar layer comprising a crystalline base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen, wherein the dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor additionally comprises first and second crystalline conductive or semiconductive oxide electrodes on opposing sides of the polar layer, wherein the polar layer has a lattice constant that is matched within about 20% of a lattice constant of one or both of the first and second crystalline conductive or semiconductive oxide electrodes. The first crystalline conductive or semiconductive oxide electrode serves as a template for growing the polar layer thereon, such that at least a portion of the polar layer is pseudomorphically formed on the first crystalline conductive or semiconductive oxide electrode.”

The patent application was filed on 2020-04-07 (16/842535).

Majority logic gate based flip-flop with non-linear polar material
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11451232) developed by Manipatruni, Sasikanth, Portland, OR, Fang, Yuan-Sheng, Oakland, CA, Menezes, Robert, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Ramesh, Ramamoorthy, Moraga, CA, and Mathuriya, Amrita, Portland, OR, for a “majority logic gate based flip-flop with non-linear polar material.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.”

The patent application was filed on 2021-07-30 (17/390830).

Ferroelectric capacitor and method of patterning such
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11430861) developed by Thareja, Gaurav, Santa Clara, CA, Manipatruni, Sasikanth, Portland, OR, Dokania, Rajeev Kumar, Beaverton, OR, Ramesh, Ramamoorthy, Moraga, CA, and Mathuriya, Amrita, Portland, OR, for “ferroelectric capacitor and method of patterning such.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.”

The patent application was filed on 2019-12-27 (16/729267).

Majority logic gate having paraelectric input capacitors and local conditioning mechanism
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11418197) developed by Dokania, Rajeev Kumar, Beaverton, OR, Mathuriya, Amrita, Portland, OR, Rios, Rafael, Austin, TX, Odinaka, Ikenna, Durham, NC, Menezes, Robert, Portland, OR, Ramesh, Ramamoorthy, Moraga, CA, and Manipatruni, Sasikanth, Portland, OR, for a “majority logic gate having paraelectric input capacitors and a local conditioning mechanism.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.”

The patent application was filed on 2021-05-21 (17/327659).

Doped polar layers and semiconductor device incorporating same
Kepler Computing Inc., San Francisco, CA, has been assigned a patent (11417768) developed by Ramamoorthy, Ramesh, Moraga, CA, Manipatruni, Sasikanth, Portland, OR, and Thareja, Gaurav, Santa Clara, CA, for “doped polar layers and semiconductor device incorporating same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer. The capacitor stack further comprises first and second barrier metal layers on respective ones of the first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.”

The patent application was filed on 2021-11-16 (17/528054).