Eideticom Awarded Two US Patents

Eideticom Communications Inc. has been assigned 2 US patents (10,996,892) for ‘Apparatus and Method for Controlling Data Acceleration,’ and (11,231,868) for ‘System and Method for Performing Computational Storage Utilizing a Hardware Accelerator.’

The abstract of the patent (10,996,892) published by the US Patent and Trademark Office states: “Systems and methods are provided that facilitate performing hardware acceleration processes without utilizing specialized drivers that are software and hardware specific by controlling the hardware accelerator with NVMe commands. The NVMe commands may be based on standardized NVMe commands provided in the NVMe spec, or may be vendor-specific commands that are supported by the NVMe spec. The commands are sent to the NVMe accelerator by a host CPU which, in some embodiments, may be located remotely to the NVMe accelerator. The NVMe accelerator may include a CMB on which a host CPU may set up an NVMe queue in order to reduce PCIe traffic on a PCIe bus connecting the CPU and the NVMe accelerator. The CMB may also be used by a host CPU to transfer data for acceleration to reduce bandwidth in the DMA controller or to remove host staging buffers and memory copies.“

The patent (10,996,892) application was filed on May 2, 2018. Inventors: Sean Gibb, Roger Bertschmann

The abstract of the patent (11,231,868) published by the US Patent and Trademark Office states: “A method, a hardware accelerator, and a system for performing computational storage utilizing a hardware accelerator device that includes a dedicated buffer memory residing on the hardware accelerator device and is connected to a CPU via a bus includes receiving, at the hardware accelerator device, computation data from the CPU computing device via the bus, performing, at the hardware accelerator device, a check pointing operation on the received computation data to generate check point data, storing the generated check point data on the dedicated buffer memory residing on the hardware accelerator device, and transmitting the check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU.“

The patent (11,231,868) application was filed on April 7, 2020. Inventors: Stephen Bates, Saeed Fouladi Fard