Radian Memory Systems Assigned Two Patents

Nonvolatile memory geometry export by memory controller
with variable host configuration of addressable memory space
Radian Memory Systems, Inc., Manhattan Beach, CA, has been assigned a patent (11,188,457) developed by Kuzmin, Andrey V., Moscow, Russia, and Wayda, James G., Laguna Niguel, CA, for a “nonvolatile memory geometry export by memory controller with variable host configuration of addressable memory space.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to ‘plan ahead’ in a manner supporting host issuance of true multi-plane read commands.”

The patent application was filed on September 13, 2019 (16/570,922).

 Erasure coding techniques for flash memory
Radian Memory Systems, Inc., Manhattan Beach, CA , has been assigned a patent (11,175,984) developed by Lercari, Robert, Thousand Oaks, CA, Robertson, Craig, Simi Valley, CA, and Jadon, Mike, Manhattan Beach, CA, for an “erasure coding techniques for flash memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This disclosure provides a memory controller for asymmetric non-volatile memory, such as flash memory, and related host and memory system architectures. The memory controller is configured to automatically generate and transmit redundancy information to a destination, e.g., a host or another memory drive, to provide for cross-drive redundancy. This redundancy information can be error (EC) information, which is linearly combined with similar information from other drives to create ‘superparity.’ If EC information is lost for one drive, it can be rebuilt by retrieving the superparity, retrieving or newly generating EC information for uncompromised drives, and linearly combining these values. In one embodiment, multiple error correction schemes are use, including a first intra-drive scheme to permit recovery of up to x structure-based failures, and the just-described redundancy scheme, to provide enhanced security for greater than x structure-based failures.”

The patent application was filed on December 9, 2019 (16/707,934).