Kioxia Assigned Twenty-Two Patents

Semiconductor memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,158,645) developed by Yamaguchi, Koichiro, Yokohama Kanagawa, Japan, for a “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a semiconductor memory device including a first memory cell, a word line, a bit line, a row decoder, a sense amplifier including a latch circuit, a data register, and a control circuit capable of suspending a write operation during the write operation of the first memory cell to perform a read operation of the first memory cell. In a read operation of the first memory cell performed while suspending the write operation, the row decoder applies a read voltage to the word line, and the sense amplifier transmits data read from the first memory cell to the data register as read data when writing to the first memory cell is completed, and transfers write data held by the latch circuit to the data register as the read data when the writing is not completed.”

The patent application was filed on January 22, 2020 (16/749,704).

Memory device
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,158,389) developed by Futatsuyama, Takuya, Yokohama Kanagawa, Japan, and Abe, Kenichi, Kawasaki Kanagawa, Japan, for a “memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer, a third conductive layer above or below the first conductive layer and on the first side of the semiconductor column, a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer, and a bit line connected to the semiconductor column. During reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage.”

The patent application was filed on March 5, 2021 (17/194,135).

Semiconductor memory device that includes block decoders each having plural transistors and latch circuit
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,158,385) developed by Kato, Koji, Yokohama Kanagawa, Japan, and Shiga, Hitoshi, Kawasaki Kanagawa, Japan, for a “semiconductor memory device that includes block decoders each having plural transistors and a latch circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory device includes a block decoder having a sense node, and a control unit. The block decoder includes first and second transistors each connected between a first node and ground, a third transistor connected between a power source voltage and a second node, a fourth transistor connected between the first and second nodes and controlled by the same gate signal as the third transistor, a fifth transistor having a first terminal connected to the sense node and a gate connected to the second node through an inverter, and a latch circuit that switches the first transistor on and off according to its setting. The control unit determines the setting of the latch circuit, according to a logic level based on a voltage of the sense node during an operation in which the second and third transistors are turned off and the fourth transistor is turned on.”

The patent application was filed on April 6, 2020 (16/841,377).

Semiconductor storage device
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,158,382) developed by Imamoto, Akihiro, and Sugahara, Akio, Yokohama Kanagawa, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device includes first and second planes each including a plurality of memory cells, an input/output circuit configured to receive data to be written in the memory cells from a controller, and a control circuit. The first plane includes a first sense amplifier circuit electrically connected to a first memory cell of the first plane and a first latch circuit connected in series between the input/output circuit and the first sense amplifier circuit. The control circuit is configured to carry out a first write operation on the first memory cell using the first latch circuit in response to a first command, and while carrying out the first write operation on the first memory cell, accept a second command to carry out a second write operation on a second memory cell of the second plane before use of the first latch circuit during the first write operation has ended.”

The patent application was filed on June 2, 2020 (16/890,849).

Memory and method for controlling
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,158,376) developed by Komatsu, Yuki, Kawasaki, Japan, Ushijima, Yasuyuki, Yokohama, Japan, and Niikura, Hisaki, Nakano, Japan, for “memory system and method for controlling memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to instruct to apply, to a first word line, a determination voltage that is based on a first value and a first difference value in a case where it is determined whether or not a first data value has been written in a first memory cell, to instruct to apply, to a second word line, a determination voltage that is based on the first value, the first difference value, and a second difference value in a case where it is determined whether or not the first data value has been written in the second memory cell, and to change the first difference value in a case where a first condition is satisfied.”

The patent application was filed on July 20, 2020 (16/932,956).

Semiconductor storage device
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,158,375) developed by Niki, Yusuke, Yokohama, Japan, for a “semiconductor storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device includes first signal lines divided into groups respectively including m, m is an integer equal to or larger than 2) of the first signal lines, and second signal lines. A memory cell array includes memory cells provided to correspond to respective intersections of the first signal lines and the second signal lines. A selection voltage is applied to any of the first signal lines through m global signal lines. First transistors are provided to respectively correspond to the first signal lines and connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups and connected to gate electrodes of the first transistors included in a corresponding one of the groups in common. First dummy signal lines are arranged between adjacent ones of the groups, to which a non-selection voltage is applied.”

The patent application was filed on February 5, 2020 (16/782,114).

Stacked type semiconductor memory and method for manufacturing
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,152,385) developed by Kato, Tatsuya, Sakamoto, Wataru, and Arai, Fumitaka, Yokkaichi, Japan, for “stacked type semiconductor memory device and method for manufacturing the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.”

The patent application was filed on February 14, 2019 (16/276,026).

Method for manufacturing semiconductor
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,152,345) developed by Tanioka, Kizashi, Yokkaichi, Japan, for a “method for manufacturing semiconductor device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to an embodiment, a method for manufacturing a semiconductor device includes forming a slit in a first wafer in which a first semiconductor layer is formed on a first substrate, sticking together the first wafer in which the slit is formed and a second wafer in which a second semiconductor layer is formed on a second substrate, the sticking being performed between a side of the first semiconductor layer and a side of the second semiconductor layer, thinning the first substrate or the second substrate of a member obtained by the sticking, forming an interconnection on a face of the substrate that is thinned, and dicing a member on which the interconnection is formed in accordance with a position of the slit.”

The patent application was filed on February 24, 2020 (16/798,797).

Semiconductor memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,152,037) developed by Hara, Hiroyuki, Fujisawa Kanagawa, Japan, Takenaka, Hiroyuki, Kamakura Kanagawa, Japan, and Chiba, Akihiko, Yokohama Kanagawa, Japan, for a “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory device includes first and second wirings extending in a first direction and spaced apart from each other in the first direction, third wirings above the first and second wirings and extending in a second direction, fourth and fifth wirings above the third wirings, extending in the first direction, and spaced apart from each other in the second direction, a plurality of memory cells between each third wiring and each of first, second, fourth, and fifth wirings, voltage application circuits, connection conductors between the voltage application circuits and the wirings, and connection wirings that electrically connect the fourth and fifth wirings to the voltage application circuits. The voltage application circuits are arranged so that a non-selected voltage application circuit is under a space between the first and second wirings, and a selected voltage application circuit is under the first wiring.”

The patent application was filed on February 27, 2020 (16/803,343).

Information processing and storage access control
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,151,064) developed by Yoshida, Hideki, Yokohama Kanagawa, Japan, for “information processing apparatus and storage device access control method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A computing device includes a memory and a processor connected to the memory and configured to: create, in a first memory space of the memory, a first I/O submission queue associated with a first application running in user space, create, in a second memory space of the memory, a second I/O submission queue associated with a second application running in user space, in response to a first I/O request from the first application, store the first I/O request in the first I/O submission queue for access by the semiconductor storage device, and in response to a second I/O request from the second application, store the second I/O request in the second I/O submission queue for access by the semiconductor storage device.”

The patent application was filed on February 6, 2020 (16/783,988).

Computing system and controlling storage device
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,151,029) developed by Kanno, Shinichi, Tokyo, Japan, for “computing system and method for controlling storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.”

The patent application was filed on January 13, 2020 (16/740,680).

Card and host
Kioxia Corp., Tokyo, Japan , has been assigned a patent (RE48,772) developed by Fujimoto, Akihisa, Fussa, Japan, for “card and host device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A host device is configured to read and write information from and into a card and to supply a supply voltage that belongs to a first voltage range or a second voltage range which is lower than the first voltage range, and issues a voltage identification command to the card. The voltage identification command includes a voltage range identification section, an error detection section, and a check pattern section. The voltage range identification section includes information indicating which one of the first voltage range and the second voltage range the supply voltage belongs. The error detection section has a pattern configured to enable the card which has received the voltage identification command to detect errors in the voltage identification command. The check pattern section has a preset pattern.”

The patent application was filed on June 24, 2019 (16/449,605).

Semiconductor memory and manufacturing
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,145,590) developed by Ode, Hiroyuki, Yokkaichi Mie, Japan, for “semiconductor memory device and method of manufacturing the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a semiconductor memory device includes: a substrate including a first area, a second area, and a third area, the second and the third areas being adjacent to the first area, a first insulating layer disposed in the first to the third areas, a first wiring disposed on a surface of the first insulating layer in the first area, a first memory cell disposed on the first wiring, a second wiring disposed on the first memory cell, and a contact connected to the second wiring in the second area. The surface of the first insulating layer includes: first surfaces disposed in at least one of the second area and the third area and arranged in the first direction, and second surfaces disposed between the first surfaces. The second surfaces are close to or far from the substrate compared with the first surfaces.”

The patent application was filed on March 5, 2020 (16/810,010).

Semiconductor memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,145,371) developed by Bushnaq, Sanad, Yokohama Kanagawa, Japan, Japan, for a “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory device comprises a memory string that includes a plurality of memory cells electrically connected in series, the memory cells including first to fourth memory cells, first to fourth word lines that are electrically connected to gates of the first to fourth memory cells, respectively, a voltage generation circuit configured to generate a first voltage, a first circuit configured to output the first voltage to one of first and second wires, a second circuit configured to connect the first and second wires to the first and second word lines, respectively, and a third circuit configured to connect the first and second wires to the third and fourth word lines, respectively.”

The patent application was filed on January 26, 2021 (17/158,321).

Memory device
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,145,346) developed by Fujino, Yorinobu, Kanagawa, Japan, for a “memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a device includes a first cell between first and second interconnects, a second cell between second and third interconnects, a third cell between fourth and fifth interconnects, a fourth cell between fifth and sixth interconnects, a equalization circuit connected to the first to sixth interconnects, and a control circuit controlling operation on the first to fourth cells. During the operation, the control circuit applies a first voltage to the first interconnect, applies a second voltage higher than the first voltage to the second interconnect, applies a third voltage to the fifth interconnect, and applies a fourth voltage higher than the third voltage to the sixth interconnect. After the operation, the equalization circuit connects the first interconnect to the sixth interconnect.”

The patent application was filed on March 11, 2020 (16/816,020).

Semiconductor and manufacturing
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,139,275) developed by Takaku, Satoru, Yokohama Kanagawa, Japan, for “semiconductor device and method of manufacturing the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a semiconductor device includes a wiring board having a first surface. A first element is disposed on the first surface of the wiring board. A first resin layer covers the first element. A second element is larger than the first element and disposed on the first resin layer. The second element is superposed above the first element. A reinforcement member is disposed at a peripheral portion of the first resin layer and includes an edge disposed inside of the first resin layer. The reinforcement member has an upper surface above the first surface of the wiring board. The reinforcement member has a coefficient of linear expansion lower than the first resin layer. An encapsulating resin material, over the first surface of the wiring board, covers the first element, the second element, the first resin layer, and the reinforcement member.”

The patent application was filed on February 24, 2020 (16/799,004).

Memory having memory cell and current detection circuit
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,139,039) developed by Kurosawa, Tomonori, Zama Kanagawa, Japan, and Nakamura, Dai, Fujisawa Kanagawa, Japan, for “memory device having memory cell and current detection circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a memory device includes a memory cell, a word line connected to the memory cell, a word line driver which generates a selection signal for the word line, a first transistor including a gate to which the selection signal generated by the word line driver is input, and a drain which supplies a signal based on the selection signal to the word line, and a detection circuit which detects a value based on a current flowing through the first transistor during a verification period after writing data to the memory cell.”

The patent application was filed on March 12, 2020 (16/816,900).

Semiconductor memory device including first memory cell and second memory cell that share well region
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,139,037) developed by Maeda, Takashi, Kanagawa, Japan, for a “semiconductor memory device including a first memory cell and a second memory cell that share a well region.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a semiconductor memory device includes: a first memory cell and a second memory cell capable of storing data and coupled in parallel to a bit line, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell and being different from the first word line, and a control circuit. The first memory cell and the second memory cell share a first well region and are opposed to each other, with the first well region interposed. The control circuit is configured, in a first operation, to repeat application of a first voltage to the first word line and the second word line a plurality of times while increasing the first voltage.”

The patent application was filed on February 6, 2020 (16/783,782).

Semiconductor storage device and memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,139,007) developed by Sato, Junichi, and Sugahara, Akio, Yokohama Kanagawa, Japan, for “semiconductor storage device and memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.”

The patent application was filed on January 19, 2021 (17/152,359).

Memory system and method performed thereby
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,138,070) developed by Kuribara, Makoto, Yokohama Kanagawa, Japan, for “memory system and method performed thereby.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “According to one embodiment, a memory system includes a non-volatile semiconductor memory having a plurality of blocks each including a plurality of memory cells, and a memory controller configured to calculate a bit error rate when reading data from a block of the blocks and obtain an equation representing temporal changes in the bit error rate for the block, and based on the obtained equation, determine, for the block, a timing for performing a next refresh operation by which data that have been written to the block are rewritten.”

The patent application was filed on February 24, 2020 (16/799,326).

Non-volatile semiconductor memory and method for driving
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,133,082) developed by Uchida, Daisuke, Fujisawa, Japan, for “non-volatile semiconductor memory device and method for driving the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The non-volatile semiconductor memory device comprises a non-volatile semiconductor memory, a controller for controlling the non-volatile semiconductor memory, the controller includes a reset terminal capable of receiving a reset signal from a host, an interface circuit capable of receiving a sleep command, and a data storing circuit, when the reset signal is received in a state which the interface circuit is being supplied with power, the data storing circuit is reset, when a sleep command is received in a state which the interface circuit is being supplied with power, the data necessary for communication with the host or the non-volatile semiconductor memory device is stored into the data storing circuit and power to the interface circuit is interrupted and when the reset signal is received in a state which power to the interface circuit is interrupted, the data is read from the data storing circuit.”

The patent application was filed on March 10, 2020 (16/813,796).

Semiconductor memory
Kioxia Corp., Tokyo, Japan , has been assigned a patent (11,133,066) developed by Shimizu, Yuki, Kamakura Kanagawa, Japan, Kamata, Yoshihiko, Yokohama Kanagawa, Japan, Kobayashi, Tsukasa, Machida Tokyo, Japan, Kataoka, Hideyuki, Kawasaki Kanagawa, Japan, Kato, Koji, Fujimoto, Takumi, Suzuki, Yoshinao, and Shimizu, Yuui, Yokohama Kanagawa, Japan, for a “semiconductor memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.”

The patent application was filed on July 21, 2020 (16/934,978).