Radian Memory Systems Assigned Three Patents

Techniques for directed data migration
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (10,552,085) developed by Chen, Alan, Robertson, Craig, Simi Valley, CA, Lercari, Robert, Thousand Oaks, CA, and Kuzmin, Andrey V., Moscow, Russia, for “techniques for directed data migration.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A host stores ‘context’ metadata for logical block addresses, (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data, in another embodiment, the context can point to other metadata.”

The patent application was filed on July 15, 2016 (15/211,939).

Techniques for delegating data processing to cooperative memory controller
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (10,552,058) developed by Jadon, Mike, Manhattan Beach, CA, Robertson, Craig, Simi Valley, CA, and Lercari, Robert, Thousand Oaks, CA, for “techniques for delegating data processing to a cooperative memory controller.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory, for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.”

The patent application was filed on July 15, 2016 (15/211,927).

Memory controller with at least one address segment defined for which data is striped across flash memory dies
Radian Memory Systems, Inc., Calabasas, CA, has been assigned a patent (10,445,229) developed by Kuzmin, Andrey V., Moscow, Russia, and Wayda, James G., Laguna Niguel, CA, for a “memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to ‘plan ahead’ in a manner supporting host issuance of true multi-plane read commands.”

The patent application was filed on June 13, 2017 (15/621,888).