Phison Assigned Twelve Patents

Data protecting and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,546,640) developed by Wu, Tsung-Lin, Tsui, Te-Chang, Hsinchu, Taiwan, and Lee, Chien-Fu, Yunlin County, Taiwan, for “data protecting method and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data protecting method and a memory storage device are provided. The data protecting method includes reading a first string from the rewritable non-volatile memory module to obtain a data string, performing a decoding operation based on the data string to obtain block information corresponding to a plurality of physical erasing units, inputting the block information to an error checking and correcting, ECC) circuit of the memory storage device to generate a second string, and storing the second string into the rewritable non-volatile memory module.”

The patent application was filed on May 10, 2017 (15/591,116).

Memory management, memory storage and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,545,700) developed by Kuo, Che-Yueh, New Taipei, Taiwan, and Li, Wen-Jin, Taipei, Taiwan, for “memory management method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: performing a data merge operation for at least one physical unit of the rewritable non-volatile memory module according to a write command from a host system, and adjusting times of performing the data merge operation according to a dispersion rate of a plurality of logical units corresponding to first data stored in at least one first-type physical unit of the rewritable non-volatile memory module.”

The patent application was filed on June 11, 2018 (16/004,444).

Decoding, memory storage and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,534,665) developed by Lin, Yu-Hsiang, Yunlin, Taiwan, Yen, Shao-Wei, Kaohsiung, Taiwan, Yang, Cheng-Che, New Taipei, Taiwan, and Lai, Kuo-Hsin, Hsinchu, Taiwan, for “memory management method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword, performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword, and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.”

The patent application was filed on January 31, 2018 (15/884,407).

Data writing, valid data identifying and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,529,426) developed by Lin, Sung-Yao, Kuo, Yueh-Pu, New Taipei, Taiwan, and Hsiao, Yu-Min, Taipei, Taiwan, for “data writing method, valid data identifying method and memory storage apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data writing method, a valid data identifying method and a memory storage apparatus using the same are provided. The method includes receiving first data, using a first programming mode to write first sub-data of the first data into a first physical programmed unit of at least a first memory sub-module of a plurality of memory sub-modules, wherein a size of each of the first sub-data is the same as a preset size, and using a second programming mode to write remaining sub-data of the first data into a second physical programmed unit of a second memory sub-module of the plurality of memory submodules, wherein the size of the remaining sub-data is less than the preset size, and the second memory sub-module is different from a third memory sub-module of the first memory submodules which is a last memory sub-module for writing the first sub-data.”

The patent application was filed on March 2, 2018 (15/910,030).

Phase-locked loop circuit calibration, memory storage and connection interface circuit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,523,223) developed by Yu, Chia-Hui, and Chen, Wei-Yung, Hsinchu County, Taiwan, for “phase-locked loop circuit calibration method, memory storage device and connection interface circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A phase-locked loop circuit calibration method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: receiving a first signal from a host system, generating a jitter signal by the memory storage device, generating a second signal according to the first signal and the jitter signal, performing a phase-lock operation on the second signal to generate a third signal by a phase-locked loop circuit, and detecting the third signal to calibrate an electronic parameter of the phase-locked loop circuit.”

The patent application was filed on May 8, 2018 (15/973,539).

Bit tagging, memory control circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,522,234) developed by Lin, Wei, Taipei, Taiwan, Lin, Yu-Hsiang, Yunlin County, Taiwan, and Hsu, Yu-Cheng, Yilan County, Taiwan, for “bit tagging method, memory control circuit unit and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits, if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits, and if the second codeword is not the valid codeword and a Y.sup.th bit in the X bits of the first codeword is different from a Y.sup.th bit in the X bits of the second codeword, recording the Y.sup.th bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.”

The patent application was filed on February 6, 2018 (15/890,326).

Memory management, memory control circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,503,433) developed by Yeh, Chih-Kang, Kinmen County, Taiwan, for “memory management method, memory control circuit unit and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The disclosure provides a memory management method, which includes: selecting at least one logical unit mapped to physical units programmed based on a first operating mode, determining a reference count according to a number of the selected logical unit, receiving a first write command, determining whether the reference count is greater than a threshold value, if the reference count is greater than the threshold value, programming first data into a first physical unit based on the first operating mode, and each memory cell in the first physical unit stores a first number of bit data, if the reference count is not greater than the threshold value, programming the first data into a second physical unit based on a second operating mode, and each memory cell in the second physical unit stores a second number of bit data, and the second number is greater than the first number.”

The patent application was filed on September 15, 2015 (14/854,059).

Memory management, memory control circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,490,283) developed by Hu, Chun-Yang, Taoyuan, Taiwan, for “memory management method, memory control circuit unit and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory management method, a memory control circuit unit and a memory storage device are provided. The method includes: performing a single-layer erasing operation on one of physical erasing units, performing a multi-layer erasing operation on another one of the physical erasing units, and performing a wear leveling operation based on the one and the another one of the physical erasing units, wherein the another one of the physical erasing units is performed the wear leveling operation first than the one of the physical erasing units.”

The patent application was filed on December 4, 2017 (15/831,319).

Memory management, memory storage device and memory controlling circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,459,630) developed by Yeh, Chih-Kang, Kinmen County, Taiwan, for “memory management method, memory storage device and memory controlling circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: defining a first data management rule for a first type physical unit and a second data management rule for a second type physical unit, and a data density of the first type physical unit is lower than the data density of the second type physical unit, if a first physical unit belongs to the first type physical unit, managing the first physical unit according to the first data management rule to make the data stored in the first physical unit conforming to a first reliability level, and if the first physical unit belongs to the second type physical unit, managing the first physical unit according to the second data management rule to make the data stored in the first physical unit conforming to a second reliability level.”

The patent application was filed on October 21, 2014 (14/519,138).

Decoding method, memory storage device and memory control circuit unit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,447,314) developed by Khon, Luong, Ho Chi Minh, Vietnam, for “decoding method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A decoding method which includes: storing first data into a buffer memory which includes a first buffer region and a second buffer region, copying decoding data in the second buffer region to the first buffer region, performing a first type decoding operation for the first data based on the copied decoding data in the first buffer region, where the copied decoding data is different from original decoding data corresponding to the first data, and outputting decoded data if the first type decoding operation is successful.”

The patent application was filed on November 7, 2017 (15/805,152).

Data accessing, memory controlling circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,445,002) developed by Lin, Wei, Liu, An-Cheng, Taipei, Taiwan, Ou, Lih Yuarn, Taoyuan, Taiwan, and Chen, Szu-Wei, New Taipei, Taiwan, for “data accessing method, memory controlling circuit unit and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data accessing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data, reading the first physical programming unit by using a second read voltage to obtain second data, inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into a numerical calculation engine, and determining a third reading voltage for reading the first physical programming unit by the numerical calculation engine.”

The patent application was filed on January 11, 2018 (15/867,719).

Data protecting, memory control circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (10,437,484) developed by Yang, Kai-Hsiang, Hsinchu County, Taiwan, for “data protecting method, memory control circuit unit and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data protecting method, a memory control circuit unit and a memory storage device are provided. The method includes repeatedly reading data from a first physical programming unit of a first physical erasing unit during an initialization operation after the memory storage device is powered on, wherein the first physical programming unit is the last programmed physical programming unit before the memory storage device is powered off. The method also includes updating a logical-physical mapping table according to the first physical programming unit if a number of error bits of data read each time is not greater than an error bits amount threshold and a reading count of the first physical programming unit is greater than a predetermined count.”

The patent application was filed on March 25, 2016 (15/080,592).