Rambus Offers Interface Solution Designed for PCIe 5.0

Rambus Inc. offers an optimized interface solution designed for PCIe 5.0, with backward compatibility to PCIe 4.0, 3.0 and 2.0.

PCIe 5.0 Interface Architecture

This PCIe 5.0 interface solution includes both PHY and digital controller for SoC integration and faster time to market.

With the PHY designed for a 7nm process node, the integrated solution offers best-in-class power, performance and area thanks to the proven engineering and signal integrity expertise of the company.

“Our high-speed SerDes and memory interface solutions make possible amazing advancements in performance-intensive applications in AI, data center, PC, storage and networking,” said Hemant Dhulla, VP and GM, IP cores, Rambus. “Now we’ve added PCIe 5 to our industry-leading portfolio of high-speed interface solutions giving chip makers another tool to unleash the power of their designs.“

In addition to the PHY, the firm’s PCIe 5.0 solution includes a performance, digital controller core from recently acquired Northwest Logic. The PHY and controller are offered as a validated and integrated solution, or they can be licensed separately and used with third-party solutions. The entire solution is backed by Rambus design, integration and support services for customers.

Benefits of PCIe 5.0 solution

Integrated and co-validated PHY and digital controller for complete interface solution
Built with the company’s design methodology for long-reach PCIe interfaces
32GT/s bandwidth per lane with 128GB/s bandwidth in x16 configuration
Backward compatible to PCIe 4.0, 3.0 and 2.0
Supports Compute Express Link interconnect
Multi-tap transceiver and receiver equalization compensate for more than 36dB of insertion loss
Best-in-class power, performance and area
Supports performance-intensive applications including AI, data center, HPC, storage and 400GbE networking