Cadence Design Systems Verification IP With Support of NVMe1.4 Protocol

Cadence Design Systems, Inc. announced the availability of Verification IP (VIP) in support of the NVMe 1.4  protocol.

Cadence VIP as NVMe Host (over PCIe)

VIP for NVMe 1.4 enables designers to verify their storage, data center and HPC SoC designs with less effort and an assurance that the SoC will meet the protocol standards. It supports the company’s Intelligent System Design strategy, enabling SoC design through IP.

It provides customers with a verification solution to develop high-quality NVMe host and device controllers, helping reduce overall time to market. It supports built-in integration with the firm’s VIP for PCIe (5.0 and includes a complete UVM SystemVerilog API for integration and SoC-level test creation. Built with the company’s TripleCheck technology, customers have access to a verification plan with measurable objectives linked to the spec features and a test suite with ready-to-run tests to ensure support for the spec.

Cadence VIP as NVMe Subsystem (over PCIe)

“The design team in our company has successfully used the Cadence VIP for NVMe while developing our products for the flash memory controller,” said Takehiko Tsuchiya, group manager, design technology group, design technology innovation division, Kioxia Corporation. “The NVMe 1.4 VIP is important for the development of the next gen of our products, supporting the need for a high-performance data interface.“

“The new NVMe 1.4 spec is designed to address the growing needs of enterprise systems that utilize PCIe-based solid-state storage,” said Moshik Rubin, director, verification IP product management group, system and verification group, Cadence. “Cadence is fully dedicated to supporting the latest standard to ensure customers have the tools they need to create differentiated end products. Our release of the first-to-market VIP for NVMe 1.4 is enabling early adopters of the protocol to reduce risk and ensure their designs comply with the spec while achieving the fastest path to IP and SoC verification closure.“

The VIP for NVMe 1.4 with TripleCheck technology is part of the firm’s Verification Suite and is optimized for Xcelium Parallel Logic Simulation, along with supported third-party simulators. The Verification Suite is comprised of core engines, verification fabric technologies that support the company’s Intelligent System Design strategy, enabling SoC design excellence.