RISC-V Summit: Western Digital Unveils Innovations to Drive Open Standard Interfaces and RISC-V Processor Development

Western Digital Corp. (WDC) announced at the RISC-V Summit three open-source innovations designed to support the company’s internal RISC-V development efforts and those of the growing RISC-V ecosystem.

In his keynote address, Martin Fink, CTO, Western Digital, unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator. These innovations are expected to accelerate development of new open, purpose-built compute architectures for big data and fast data environments.

The company has taken an active role in helping to advance the RISC-V ecosystem, including multiple related strategic investments and partnerships, and demonstrated progress toward its stated goal of transitioning one billion of the company’s processor cores to the RISC-V architecture.

“As big data and fast data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today’s wide-ranging data-centric applications,” said Fink. “Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realized by bringing data closer to processing power. These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries.“

RISC-V is an open, scalable instruction set architecture that enables the diversity of big data and fast data applications and workloads proliferating in core data centers and in remote and mobile systems at the edge. It provides an alternative to current, standard, general purpose compute architectures. With RISC-V, open standard interfaces can be utilized to enable specialty processing, memory centric solutions, unique storage and flexible interconnect applications.

The company is planning to open source its RISC-V SweRV Core, which has a two-way superscalar design. The RISC-V SweRV Core is a 32-bit, nine stage pipeline core that allows several instructions to be loaded at once and execute simultaneously, shortening the time taken to run programs.

It is a compact, in-order core and runs at 4.9 CoreMarks/Mhz ⁽¹⁾. Its power-efficient design offers clock speeds of up to 1.8Ghz ⁽¹⁾ on a 28mm CMOS process technology. The company plans to use the SweRV Core in various internal embedded designs, including flash controllers and SSDs. Open sourcing the core is expected to drive development of data-centric applications such as IoT, secure processing, industrial controls and more.

The firm’s OmniXtend is an open approach to providing cache coherent memory over an Ethernet fabric. This memory-centric system architecture provides open standard interfaces for access and data sharing across processors, machine learning accelerators, GPUs, FPGAs and other components. It is an open solution for efficiently attaching persistent memory to processors and offers potential support of future advanced fabrics that connect compute, storage, memory and I/O components.

The company also introduced today its open-sourced SweRV Instruction Set Simulator (ISS), which offers test bench support for use with RISC-V cores. An ISS is a computer program that simulates the execution of instructions of a processor. It allows external events to be modeled, such as interrupts and bus errors, and assures the RISC-V core is functioning properly. The company utilized the SweRV ISS to simulate and validate the SweRV Core, with more than ten billion instructions executed. Western Digital expects both the SweRV Core and SweRV ISS will help to accelerate the industry’s move to an open source instruction set architecture.

“Speeds, feeds, and brute compute is no longer the winning formula for edge and endpoint computing. As more data moves to the edge for real-time processing and inferencing, configurable architectures will be better suited to meet the needs of heavy and often dynamic application workloads, especially for those driven by artificial intelligence and IoT,” said Mario Morales, program VP, enabling technologies and semiconductors, IDC. “Power efficiency, configurability, and low power will become the key metrics for edge and endpoint computing architectures.“

Availability and ressources:

• SweRV ISS and OmniXtend architecture are available for download at the following locations:

  • • • OmniXtend

      • SweRV ISS

• SweRV core will be available in 1Q19.

⁽¹⁾ Estimated performance based on internal testing.

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Resources:
Download Technology Brief
Download SweRV ISS to validate your RISC-V core